HD6417750RF240DV Renesas Electronics America, HD6417750RF240DV Datasheet - Page 967

• Manufacturer Part Number: HD6417750RF240DV
• Description: MPU 3V 16K I-TEMP,PB-FREE 208-QF
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF240DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

21.1.3
Table 21.1 shows the H-UDI pin configuration.
Table 21.1 H-UDI Pins
Pin Name
Clock pin
Mode pin
Reset pin
Data input
pin
Data output
pin
Emulator pin
Notes: 1. Pulled up inside the chip. When designing a board that allows use of an emulator, or
2. When designing a board that enables the use of an emulator, or when using interrupts
3. Fixed to the ground or connected to the same signal line as RESET, or to a signal line
Pin Configuration
when using interrupts and resets via the H-UDI, there is no problem in connecting a
pullup resistance externally.
and resets via the H-UDI, drive TRST low for a period overlapping RESET at power-on,
and also provide for control by TRST alone.
that behaves in the same way. However, there is a problem when this pin is fixed to the
ground. TRST is pulled up in the chip so, when this pin is fixed to the ground via
external connection, a minute current will flow. The size of this current is determined by
Abbreviation I/O
TCK
TMS
TRST
TDI
TDO
ASEBRK/
BRKACK
Input
Input
Input
Input
Output The data output pin. Data is sent to the H-UDI
Input/
output
Section 21 High-performance User Debug Interface (H-UDI)
Function
Same as the JTAG serial clock input pin. Data
is transferred from data input pin TDI to the H-
UDI circuit, and data is read from data output
pin TDO, in synchronization with this signal.
The mode select input pin. Changing this
signal in synchronization with TCK determines
the meaning of the data input from TDI. The
protocol conforms to the JTAG (IEEE Std
1149.1) specification.
The input pin that resets the H-UDI. This signal
is received asynchronously with respect to
TCK, and effects a reset of the JTAG interface
circuit when low. TRST must be driven low for
a certain period when powering on, regardless
of whether or not JTAG is used. This differs
from the IEEE specification.
The data input pin. Data is sent to the H-UDI
circuit by changing this signal in
synchronization with TCK.
circuit by reading this signal in synchronization
with TCK.
Dedicated emulator pin
Rev.7.00 Oct. 10, 2008 Page 881 of 1074
REJ09B0366-0700
When Not
Used
Open *
Open *
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Open
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