HD6417750RF240DV Renesas Electronics America, HD6417750RF240DV Datasheet - Page 373

• Manufacturer Part Number: HD6417750RF240DV
• Description: MPU 3V 16K I-TEMP,PB-FREE 208-QF
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF240DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

10.1
The on-chip oscillation circuits comprise a clock pulse generator (CPG) and a watchdog timer
(WDT).
The CPG generates the clocks supplied inside the processor and performs power-down mode
control.
The WDT is a single-channel timer used to count the clock stabilization time when exiting standby
mode or the frequency is changed. It can be used as a normal watchdog timer or an interval timer.
10.1.1
The CPG has the following features:
• Three clocks
• Six clock modes
• Frequency change function
• PLL on/off control
• Power-down mode control
The CPG can generate the CPU clock (Ick) used by the CPU, FPU, caches, and TLB, the
peripheral module clock (Pck) used by the peripheral modules, and the bus clock (Bck) used
by the external bus interface.
Any of six clock operating modes can be selected, with different combinations of CPU clock,
bus clock, and peripheral module clock division ratios after a power-on reset.
PLL (phase-locked loop) circuits and a frequency divider in the CPG enable the CPU clock,
bus clock, and peripheral module clock frequencies to be changed independently. Frequency
changes are performed by software in accordance with the settings in the frequency control
register (FRQCR).
Power consumption can be reduced by stopping the PLL circuits during low-frequency
operation.
It is possible to stop the clock in sleep mode and standby mode, and to stop specific modules
with the module standby function.
Features
Overview
Section 10 Clock Oscillation Circuits
Rev.7.00 Oct. 10, 2008 Page 287 of 1074
Section 10 Clock Oscillation Circuits
REJ09B0366-0700