HD6417750RF240DV Renesas Electronics America, HD6417750RF240DV Datasheet - Page 865

MPU 3V 16K I-TEMP,PB-FREE 208-QF

HD6417750RF240DV

Manufacturer Part Number
HD6417750RF240DV
Description
MPU 3V 16K I-TEMP,PB-FREE 208-QF
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of HD6417750RF240DV

Core Processor
SH-4
Core Size
32-Bit
Speed
240MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
28
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
208-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417750RF240DV
Manufacturer:
HITACHI
Quantity:
7 287
Bit 0—Smart Card Interface Mode Select (SMIF): Enables or disables the smart card interface
function.
Bit 0: SMIF
0
1
17.2.2
Bit 7 of SCSMR1 has a different function in smart card interface mode.
Bit 7—GSM Mode (GM): Sets the smart card interface function to GSM mode.
With the normal smart card interface, this bit is cleared to 0. Setting this bit to 1 selects GSM
mode, an additional mode for controlling the timing for setting the TEND flag that indicates
completion of transmission, and the type of clock output used. The details of the additional clock
output control mode are specified by the CKE1 and CKE0 bits in the serial control register
(SCSCR1). In GSM mode, the pulse width is guaranteed when SCK start/stop specifications are
made by CKE1 and CKE0.
Bit 7: GM
0
1
Note: etu: Elementary time unit (time for transfer of 1 bit)
Initial value:
Serial Mode Register (SCSMR1)
R/W:
Bit:
GM(C/A)
Description
Smart card interface function is disabled
Smart card interface function is enabled
Description
Normal smart card interface mode operation
GSM mode smart card interface mode operation
R/W
7
0
The TEND flag is set 12.5 etu after the beginning of the start bit
Clock output on/off control only
The TEND flag is set 11.0 etu after the beginning of the start bit
Clock output on/off and fixed-high/fixed-low control (set in SCSCR1)
CHR
R/W
6
0
R/W
PE
5
0
R/W
O/E
4
0
Rev.7.00 Oct. 10, 2008 Page 779 of 1074
STOP
R/W
3
0
Section 17 Smart Card Interface
R/W
MP
2
0
REJ09B0366-0700
CKS1
R/W
1
0
(Initial value)
(Initial value)
CKS0
R/W
0
0

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