HD6417750RF240DV Renesas Electronics America, HD6417750RF240DV Datasheet - Page 583

• Manufacturer Part Number: HD6417750RF240DV
• Description: MPU 3V 16K I-TEMP,PB-FREE 208-QF
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF240DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 13 Bus State Controller (BSC)
13.3.6
Burst ROM Interface
Setting bits A0BST2–A0BST0, A5BST2–A5BST0, and A6BST2–A6BST0 in BCR1 to a non-
zero value allows burst ROM to be connected to areas 0, 5, and 6. The burst ROM interface
provides high-speed access to ROM that has a burst access function. The timing for burst access to
burst ROM is shown in figure 13.47. Two wait cycles are set. Basically, access is performed in the
same way as for SRAM interface, but when the first cycle ends, only the address is changed before
the next access is executed. When 8-bit ROM is connected, the number of consecutive accesses
can be set as 4, 8, 16, or 32 with bits A0BST2–A0BST0, A5BST2–A5BST0, or A6BST2–
A6BST0. When 16-bit ROM is connected, 4, 8, or 16 can be set in the same way. When 32-bit
ROM is connected, 4 or 8 can be set.
RDY pin sampling is always performed when one or more wait states are set.
The second and subsequent access cycles also comprise two cycles when a burst ROM setting is
made and the wait specification is 0. The timing in this case is shown in figure 13.48.
A write operation for the burst ROM interface is performed as if the SRAM interface is selected.
In 32-byte transfer, a total of 32 bytes are transferred consecutively according to the set bus width.
The first access is performed on the data for which there was an access request, and the remaining
accesses are performed on the data at the 32-byte boundary. The bus is not released during this
period.
Figure 13.49 shows the timing when a burst ROM setting is made, and setup/hold is specified in
WCR3.
Rev.7.00 Oct. 10, 2008 Page 497 of 1074
REJ09B0366-0700