HD6417750RF240DV Renesas Electronics America, HD6417750RF240DV Datasheet - Page 853

• Manufacturer Part Number: HD6417750RF240DV
• Description: MPU 3V 16K I-TEMP,PB-FREE 208-QF
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF240DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

In serial reception, the SCIF operates as described below.
1. The SCIF monitors the transmission line, and if a 0 start bit is detected, performs internal
2. The received data is stored in SCRSR2 in LSB-to-MSB order.
3. The parity bit and stop bit are received.
4. If the RIE bit in SCSCR2 is set to 1 when the RDF or DR flag changes to 1, a receive-FIFO-
synchronization and starts reception.
After receiving these bits, the SCIF carries out the following checks.
a. Stop bit check: The SCIF checks whether the stop bit is 1. If there are two stop bits, only
b. The SCIF checks whether receive data can be transferred from the receive shift register
c. Overrun error check: The SCIF checks that the ORER flag is 0, indicating that no overrun
d. Break check: The SCIF checks that the BRK flag is 0, indicating that the break state is not
data-full interrupt (RXI) request is generated.
If the RIE bit or REIE bit in SCSCR2 is set to 1 when the ER flag changes to 1, a receive-error
interrupt (ERI) request is generated.
If the RIE bit or REIE bit in SCSCR2 is set to 1 when the BRK or ORER flag changes to 1, a
break reception interrupt (BRI) request is generated.
Note: Reception continues when parity error, framing error occurs.
the first is checked.
(SCRSR2) to SCFRDR2.
error has occurred.
set.
If b, c, and d checks are passed, the receive data is stored in SCFRDR2.
Section 16 Serial Communication Interface with FIFO (SCIF)
Rev.7.00 Oct. 10, 2008 Page 767 of 1074
REJ09B0366-0700