HD6417750RF240DV Renesas Electronics America, HD6417750RF240DV Datasheet - Page 851

MPU 3V 16K I-TEMP,PB-FREE 208-QF

HD6417750RF240DV

Manufacturer Part Number
HD6417750RF240DV
Description
MPU 3V 16K I-TEMP,PB-FREE 208-QF
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of HD6417750RF240DV

Core Processor
SH-4
Core Size
32-Bit
Speed
240MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
28
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
208-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417750RF240DV
Manufacturer:
HITACHI
Quantity:
7 287
Serial Data Reception: Figure 16.10 shows a sample flowchart for serial reception.
Use the following procedure for serial data reception after enabling the SCIF for reception.
No
No
Clear RE bit in SCSCR2 to 0
Read ER, DR, BRK flags in
Read RDF flag in SCFSR2
SCFRDR2, and clear RDF
ER or DR or BRK or ORER
Read receive data in
SCFSR2 and ORER
flag in SCFSR2 to 0
All data received?
Start of reception
End of reception
flag in SCLSR2
Figure 16.10 Sample Serial Reception Flowchart (1)
RDF = 1?
= 1?
No
Yes
Yes
Section 16 Serial Communication Interface with FIFO (SCIF)
Error handling
Yes
Rev.7.00 Oct. 10, 2008 Page 765 of 1074
1. Receive error handling and
2. SCIF status check and receive
3. Serial reception continuation
break detection: Read the DR,
ER, and BRK flags in
SCFSR2, and the ORER flag
in SCLSR2, to identify any
error, perform the appropriate
error handling, then clear the
DR, ER, BRK, and ORER
flags to 0. In the case of a
framing error, a break can also
be detected by reading the
value of the RxD2 pin.
data read : Read SCFSR2 and
check that RDF = 1, then read
the receive data in SCFRDR2,
read 1 from the RDF flag, and
then clear the RDF flag to 0.
The transition of the RDF flag
from 0 to 1 can also be
identified by an RXI interrupt.
procedure: To continue serial
reception, read at least the
receive trigger set number of
receive data bytes from
SCFRDR2, read 1 from the
RDF flag, then clear the RDF
flag to 0. The number of
receive data bytes in
SCFRDR2 can be ascertained
by reading the lower bits of
SCFDR2.
REJ09B0366-0700

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