HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 1170

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Rev. 2.00 Feb. 12, 2010 Page 1086 of 1330
REJ09B0554-0200
Bit
12
11 to 9
8
7 to 1
0
Bit Name
VINTSEL
⎯
VINTE
⎯
VINTS
Initial Value
0
All 0
0
All 0
0
R/W
R/W
R
R/W
R
R/W
Description
Vsync Interrupt Select
Sets the starting point of the LCDC's Vsync
interrupt.
0: Vsync interrupt occurs at the beginning of access
1: Vsync interrupt occurs at the beginning of the
Reserved
These bits are always read as 0. The write value
should always be 0.
Vsync Interrupt Enable
Sets whether or not to generate LCDC's Vsync
interrupts.
0: Vsync interrupts are disabled
1: Vsync interrupts are enabled
Reserved
These bits are always read as 0. The write value
should always be 0.
Vsync Interrupt State
Indicates the LCDC's Vsync interrupt handling
state. This bit is set to 1 at the time a Vsync
interrupt is generated. During the processing
routine for Vsync interrupt, clear the register by
entering a value of 0.
0: LCDC did not generate a Vsync interrupt or has
1: LCDC has generated a Vsync interrupt and has
When Vsync interrupts are enabled, the VINTE bit
must be set to 1 before the DON bit is set to 1, and
the VINTE bit must not be cleared to 0.
When the VINTE bit is set to 0, Vsync interrupts are
not generated.
to synchronous DRAM
LCD display vertical retrace period
been informed that the generated Vsync
interrupt has completed
not yet been informed that the generated Vsync
interrupt has completed