HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 759
HD6417760BL200AV
Manufacturer Part Number
HD6417760BL200AV
Description
SH4 7760, 17 X17 256BGA, LCDC, U
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417760BP200ADV.pdf
(1418 pages)
Specifications of HD6417760BL200AV
Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
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Quantity
Price
Company:
Part Number:
HD6417760BL200AV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD6417760BL200AV
Manufacturer:
RENENAS
Quantity:
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19.3.6
The status bits of the master status register (bits 0 to 6) are cleared by writing 0 to the respective
status bit positions in the reception states. Each status bit remains 1 until reset by writing 0.
Initial value:
Initial value:
Bit
31 to 7
6
5
4
R/W:
R/W:
Bit:
Bit:
Master Status Register (ICMSR)
Bit Name
⎯
MNR
MAL
MST
31
15
R
R
0
0
-
-
30
14
R
R
-
-
0
0
29
13
R
R
0
0
-
-
Initial Value
All 0
0
0
0
28
12
R
R
0
0
-
-
27
11
R
R
0
0
-
-
R
R/W*
R/W*
R/W
R/W*
26
10
R
R
-
0
-
0
25
R
R
-
0
9
-
0
Description
Reserved
These bits are always read as 0, and the write
value should always be 0.
Master NACK Received
MNR = 1 indicates that the master has received a
NACK response (SDA is high during the
acknowledge cycle on the bus) during an address
or data transmission.
Master Arbitration Lost
MAL = 1 in the multiple-master system indicates
that the master has lost bus arbitration for other
masters. In this case, MIE is reset and master
interface is disabled.
Master Stop Transmission
MST = 1 indicates that the master has sent a stop
onto the bus. A stop can be sent either as a result
of the setting of the forced stop bit in the control
register, or from a NACK being received from a
slave during data packet reception from a slave.
24
R
R
0
8
0
-
-
23
R
R
0
7
0
-
-
Rev. 2.00 Feb. 12, 2010 Page 675 of 1330
MNR
R/W* R/W* R/W* R/W* R/W* R/W* R/W*
22
R
0
0
6
-
MAL
21
R
0
5
0
-
MST
20
Section 19 I
R
4
0
0
-
MDE
19
R
0
3
0
-
REJ09B0554-0200
MDT
18
R
0
2
0
-
2
C Bus Interface
MDR
17
R
0
1
0
-
MAT
16
R
0
0
0
-
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