HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 212
HD6417760BL200AV
Manufacturer Part Number
HD6417760BL200AV
Description
SH4 7760, 17 X17 256BGA, LCDC, U
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417760BP200ADV.pdf
(1418 pages)
Specifications of HD6417760BL200AV
Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417760BL200AV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD6417760BL200AV
Manufacturer:
RENENAS
Quantity:
20 000
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6.3
6.3.1
The UTLB is used for the following two purposes:
1. To translate a virtual address to a physical address in a data access
2. As a table of address translation information to be recorded in the ITLB in the event of an
The UTLB is so called because of its use for the above two purposes. Information in the address
translation table located in external memory is cached into the UTLB. The address translation
table contains virtual page numbers and address space identifiers, and corresponding physical page
numbers and page management information. Figure 6.6 shows the UTLB configuration. The
UTLB consists of 64 fully-associative type entries. Figure 6.7 shows the relationship between the
page size and address format.
Rev. 2.00 Feb. 12, 2010 Page 128 of 1330
REJ09B0554-0200
ITLB miss
Entry 0
Entry 1
Entry 2
Entry 63
TLB Functions
Unified TLB (UTLB) Configuration
• 1-Kbyte page
• 4-Kbyte page
• 64-Kbyte page
• 1-Mbyte page
Figure 6.7 Relationship between Page Size and Address Format
31
31
31
31
ASID [7:0]
ASID [7:0]
ASID [7:0]
ASID [7:0] VPN [31:10] V
VPN
VPN
VPN
VPN
20 19
Virtual address
Virtual address
Virtual address
Virtual address
VPN [31:10]
VPN [31:10]
VPN [31:10]
16 15
Figure 6.6 UTLB Configuration
12 11
10 9
Offset
Offset
V
V
V
Offset
Offset
PPN [28:10]
PPN [28:10]
PPN [28:10]
PPN [28:10] SZ [1:0] SH C PR [1:0]
0
0
0
0
SZ [1:0]
SZ [1:0]
SZ [1:0]
28
28
28
28
PPN
SH
SH
SH
PPN
PPN
Physical address
PPN
Physical address
Physical address
Physical address
20 19
C
C
C
PR [1:0]
PR [1:0]
PR [1:0]
16 15
12 11
10 9
Offset
D
D
D
D WT
Offset
WT
WT
WT
Offset
Offset
SA [2:0]
SA [2:0]
SA [2:0]
SA [2:0] TC
0
0
0
0
TC
TC
TC
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