HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 690
HD6417760BL200AV
Manufacturer Part Number
HD6417760BL200AV
Description
SH4 7760, 17 X17 256BGA, LCDC, U
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417760BP200ADV.pdf
(1418 pages)
Specifications of HD6417760BL200AV
Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
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Company:
Part Number:
HD6417760BL200AV
Manufacturer:
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(2) Clock
Either an internal clock generated by the on-chip baud rate generator or an external clock input at
the SCIF_CLK pin can be selected as the SCIF's serial clock, according to the settings of the C/A
bit in SCSMR and the CKE1 and CKE0 bits in SCSCR. For details of SCIF clock source
selection, see table 17.5.
When an external clock is input at the SCIF_CLK pin, the clock frequency should be 16 times the
bit rate used.
When the SCIF is operated on an internal clock, a clock whose frequency is 16 times the bit rate is
output from the SCIF_CLK pin.
(3) SCIF Initialization (Asynchronous Mode)
Before transmitting and receiving data, it is necessary to clear the TE and RE bits in SCSCR to 0,
then initialize the SCIF as described below.
When the operating mode or transfer format, etc., is changed, the TE and RE bits must be cleared
to 0 before making the change using the following procedure.
1.
2.
3.
Rev. 2.00 Feb. 12, 2010 Page 606 of 1330
REJ09B0554-0200
When the TE bit is cleared to 0, SCTSR is initialized. Note that clearing the TE and RE bits to
0 does not change the contents of SCFSR, SCFTDR, or SCFRDR.
The TE bit should be cleared to 0 after all transmit data has been sent and the TEND flag in
SCFSR has been set. TEND can also be cleared to 0 during transmission, but the data being
transmitted will go to the mark state after the clearance. Before setting TE again to start
transmission, the TFRST bit in SCFCR should first be set to 1 to reset SCFTDR.
When an external clock is used the clock should not be stopped during operation, including
initialization, since operation will be unreliable in this case.
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