HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 248
HD6417760BL200AV
Manufacturer Part Number
HD6417760BL200AV
Description
SH4 7760, 17 X17 256BGA, LCDC, U
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417760BP200ADV.pdf
(1418 pages)
Specifications of HD6417760BL200AV
Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
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Company:
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7.3.8
This LSI supports a prefetch instruction to reduce the cache fill penalty incurred as the result of a
cache miss. If it is known that a cache miss will result from a read or write operation, it is possible
to fill the cache with data beforehand by means of the prefetch instruction to prevent a cache miss
due to the read or write operation, and so improve software performance. If a prefetch instruction
is executed for data already held in the cache, or if the prefetch address results in a UTLB miss or
a protection violation, the result is no operation, and an exception is not generated. Details of the
prefetch instruction are given in the Programming Manual.
• Prefetch instruction
7.3.9
When cache enhanced mode (CCR.EMODE = 1) is specified and OC RAM mode (CCR.ORA =
1) is selected, in which half of the operand cache is used as internal RAM, internal RAM data may
be updated incorrectly.
Conditions Under which Problem Occurs: Incorrect data may be written to RAM when the
following four conditions are satisfied.
Condition 1: Cache enhanced mode (CCR.EMODE = 1) is specified.
Condition 2: The RAM mode (CCR.ORA = 1) in which half of the operand cache is used as
Condition 3: An exception or an interrupt occurs.
Note: This includes a break triggered by a debugging tool swapping an instruction (a break
Condition 4: A store instruction (MOV, FMOV, AND.B, OR, B, XOR.B, MOVCA.L, STC.L, or
Description: When the problem occurs, 8 bytes of incorrect data is written to the 8-byte boundary
that includes an address that differs by H'2000 from the address accessed by the store instruction
that accesses internal RAM mentioned in condition 4. For example, when a long word is stored at
address H'7C000204, the 8 bytes of data in the internal RAM mapped to addresses H'7C002200 to
H'7C002207 becomes corrupted.
Rev. 2.00 Feb. 12, 2010 Page 164 of 1330
REJ09B0554-0200
occurring when a TRAPA instruction or undefined instruction code H'FFFD is swapped
for an instruction).
Prefetch Operation
Note on Using Cache Enhanced Mode
internal RAM is specified.
STS.L) that accesses internal RAM (H'7C000000 to H'7FFFFFFF) exists within four
instructions after the instruction associated with the exception or interrupt described
in condition 3. This includes cases where the store instruction that accesses internal
RAM itself generates an exception.
: PREF @Rn
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