HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 676
HD6417760BL200AV
Manufacturer Part Number
HD6417760BL200AV
Description
SH4 7760, 17 X17 256BGA, LCDC, U
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417760BP200ADV.pdf
(1418 pages)
Specifications of HD6417760BL200AV
Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
HD6417760BL200AV
Manufacturer:
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Quantity:
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Part Number:
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Manufacturer:
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Quantity:
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etu: Elementary time unit (time for transfer of 1 bit)
Notes: 1. Only 0 can be written, to clear the flag.
Rev. 2.00 Feb. 12, 2010 Page 592 of 1330
REJ09B0554-0200
Bit
0
2. When a break is detected, the receive data (H'00) following detection is not transferred
3. SCFRDR is a 128-byte FIFO register. When RDF = 1, at least the receive trigger set
4. Equivalent to 1.5 frames with an 8-bit, 1-stop-bit format.
Bit Name
DR
to SCFRDR. When the break ends and the receive signal returns to mark "1", receive
data transfer is resumed.
number of data bytes can be read. If all the data in SCFRDR is read and another read
is performed, the data value will be undefined. The number of receive data bytes in
SCFRDR is indicated by SCRFDR.
Initial Value
0
R/W
R/W*
1
Description
Receive Data Ready
In asynchronous mode, indicates that there are
fewer than the receive trigger set number of data
bytes in SCFRDR, and no further data has
arrived for at least 15 etu after the stop bit of the
last data received. This is not set when using
synchronous mode.
0: Reception is in progress or has ended normally
[Clearing conditions]
•
•
•
1: No further receive data has arrived
[Setting condition]
•
and there is no receive data left in SCFRDR
Power-on reset or manual reset
When all the receive data in SCFRDR has
been read after reading DR = 1, and 0 is
written to DR
When all the receive data in SCFRDR has
been read by the DMAC
When SCFRDR contains fewer than the
receive trigger set number of receive data
bytes, and no further data has arrived for at
least 15 etu after the stop bit of the last data
received*
4
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