SAK-XC886-8FFA 5V AC Infineon Technologies, SAK-XC886-8FFA 5V AC Datasheet - Page 36
![IC MCU 8BIT FLASH 48-TQFP](/photos/16/13/161323/qfp48_sml.jpg)
SAK-XC886-8FFA 5V AC
Manufacturer Part Number
SAK-XC886-8FFA 5V AC
Description
IC MCU 8BIT FLASH 48-TQFP
Manufacturer
Infineon Technologies
Series
XC8xxr
Datasheet
1.SAF-XC888CLM-6FFA_5V_AC.pdf
(144 pages)
Specifications of SAK-XC886-8FFA 5V AC
Core Processor
XC800
Core Size
8-Bit
Speed
103.2MHz
Connectivity
SSI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.75K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-TFQFP
Data Bus Width
8 bit
Data Ram Size
1.75 KB
Interface Type
UART, SSC
Maximum Clock Frequency
24 MHz
Number Of Programmable I/os
34
Number Of Timers
4
Operating Supply Voltage
5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
For Use With
B158-H8743-X-X-7600IN - KIT STARTER XC886/888B158-H8576-X-0-7600IN - KIT EASY XC866B158-H8548-X-0-7600IN - KIT STARTER XC866
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
SP000210971
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- Download datasheet (2Mb)
Field
OP
0
3.2.3
The bit protection scheme prevents direct software writing of selected bits (i.e., protected
bits) using the PASSWD register. When the bit field MODE is 11
bit field PASS opens access to writing of all protected bits, and writing 10101
field PASS closes access to writing of all protected bits. In both cases, the value of the
bit field MODE is not changed even if PASSWD register is written with 98
only be changed when bit field PASS is written with 11000
PASSWD register disables the bit protection scheme.
Note that access is opened for maximum 32 CCLKs if the “close access” password is not
written. If “open access” password is written again before the end of 32 CCLK cycles,
there will be a recount of 32 CCLK cycles. The protected bits include the N- and K-
Divider bits, NDIV and KDIV; the Watchdog Timer enable bit, WDTEN; and the power-
down and slow-down enable bits, PD and SD.
Data Sheet
Bit Protection Scheme
Bits
[7:6]
3
Type Description
w
r
Operation
0X
10
11
Reserved
Returns 0 if read; should be written with 0.
Manual page mode. The value of STNR is
ignored and PAGE is directly written.
New page programming with automatic page
saving. The value written to the bit positions of
PAGE is stored. In parallel, the previous
contents of PAGE are saved in the storage bit
field STx indicated by STNR.
Automatic restore page action. The value
written to the bit positions PAGE is ignored
and instead, PAGE is overwritten by the
contents of the storage bit field STx indicated
by STNR.
29
B
, for example, writing D0
Functional Description
B
, writing 10011
XC886/888CLM
H
or A8
V1.2, 2009-07
B
to the bit
H
B
. It can
to the
H
to
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