SAK-XC886-8FFA 5V AC Infineon Technologies, SAK-XC886-8FFA 5V AC Datasheet - Page 46
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SAK-XC886-8FFA 5V AC
Manufacturer Part Number
SAK-XC886-8FFA 5V AC
Description
IC MCU 8BIT FLASH 48-TQFP
Manufacturer
Infineon Technologies
Series
XC8xxr
Datasheet
1.SAF-XC888CLM-6FFA_5V_AC.pdf
(144 pages)
Specifications of SAK-XC886-8FFA 5V AC
Core Processor
XC800
Core Size
8-Bit
Speed
103.2MHz
Connectivity
SSI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.75K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-TFQFP
Data Bus Width
8 bit
Data Ram Size
1.75 KB
Interface Type
UART, SSC
Maximum Clock Frequency
24 MHz
Number Of Programmable I/os
34
Number Of Timers
4
Operating Supply Voltage
5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
For Use With
B158-H8743-X-X-7600IN - KIT STARTER XC886/888B158-H8576-X-0-7600IN - KIT EASY XC866B158-H8548-X-0-7600IN - KIT STARTER XC866
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
SP000210971
Table 10
Addr Register Name
93 H
B0 H
B1 H
C8 H
C9 H
RMAP = 0, PAGE 3
80 H
90 H
92 H
B0 H
C8 H
3.2.4.7
The ADC SFRs can be accessed in the standard memory area (RMAP = 0).
Table 11
Addr Register Name
RMAP = 0
D1 H
RMAP = 0, PAGE 0
CA H
CB H
CC H
Data Sheet
P5_ALTSEL1
P5 Alternate Select 1 Register
P3_ALTSEL0
P3 Alternate Select 0 Register
P3_ALTSEL1
P3 Alternate Select 1 Register
P4_ALTSEL0
P4 Alternate Select 0 Register
P4_ALTSEL1
P4 Alternate Select 1 Register
P0_OD
P0 Open Drain Control Register
P1_OD
P1 Open Drain Control Register
P5_OD
P5 Open Drain Control Register
P3_OD
P3 Open Drain Control Register
P4_OD
P4 Open Drain Control Register
ADC_PAGE
Page Register
ADC_GLOBCTR Reset: 30 H
Global Control Register
ADC_GLOBSTR Reset: 00 H
Global Status Register
ADC_PRAR
Priority and Arbitration Register
ADC Registers
Port Register Overview (cont’d)
ADC Register Overview
Reset: 00 H
Reset: 00 H
Reset: 00 H
Reset: 00 H
Reset: 00 H
Reset: 00 H
Reset: 00 H
Reset: 00 H
Reset: 00 H
Reset: 00 H
Reset: 00 H
Reset: 00 H
Bit
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
ANON
ASEN
P7
P7
P7
P7
P7
P7
P7
P7
P7
P7
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
7
7
1
OP
w
0
r
39
ASEN
DW
P6
P6
P6
P6
P6
P6
P6
P6
P6
P6
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
6
6
0
P5
P5
P5
P5
P5
P5
P5
P5
P5
P5
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
5
5
0
r
STNR
CTC
rw
w
CHNR
ARBM
P4
P4
P4
P4
P4
P4
P4
P4
P4
P4
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rh
4
4
Functional Description
CSM1
P3
P3
P3
P3
P3
P3
P3
P3
P3
P3
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
3
3
0
r
PRIO1
XC886/888CLM
P2
P2
P2
P2
P2
P2
P2
P2
P2
P2
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
2
2
0
r
0
r
V1.2, 2009-07
PAGE
SAMP
CSM0
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
LE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
1
rh
1
PRIO0
BUSY
P0
P0
P0
P0
P0
P0
P0
P0
P0
P0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
rh
0