UPD78F1143AGK-GAJ-AX Renesas Electronics America, UPD78F1143AGK-GAJ-AX Datasheet - Page 306
![no-image](/images/manufacturer_photos/0/5/560/renesas_electronics_america_sml.jpg)
UPD78F1143AGK-GAJ-AX
Manufacturer Part Number
UPD78F1143AGK-GAJ-AX
Description
MCU 16BIT 78K0R/KX3 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet
1.UPD78F1142AGA-HAB-AX.pdf
(880 pages)
Specifications of UPD78F1143AGK-GAJ-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
96KB (96K x 8)
Program Memory Type
FLASH
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1143AGK-GAJ-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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<R>
<R>
(2) A/D converter mode register (ADM)
304
Note To stabilize the internal circuit, the time from the rising of the ADCE bit to the falling of the ADCS bit must be
Caution A/D conversion must be stopped before rewriting bits FR0 to FR2, LV1, and LV0 to values other
This register sets the conversion time for analog input to be A/D converted, and starts/stops conversion.
ADM can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Notes 1.
1
Symbol
Address: FFF30H
μ
2.
ADM
s or longer.
than the identical data.
ADCS
0
0
1
1
For details of FR2 to FR0, LV1, LV0, and A/D conversion, see Table 10-3 A/D Conversion Time
Selection.
The operation of the A/D voltage comparator is controlled by ADCS and ADCE, and it takes 1
operation start to operation stabilization. Therefore, when ADCS is set to 1 after 1
elapsed from the time ADCE is set to 1, the conversion result at that time has priority over the first
conversion result. Otherwise, ignore data of the first conversion.
ADCS
ADCE
ADCS
<7>
0
1
0
1
Figure 10-5. Timing Chart When A/D voltage Comparator Is Used
A/D voltage
comparator
ADCE
Figure 10-4. Format of A/D Converter Mode Register (ADM)
0
1
0
1
ADCE
ADCS
After reset: 00H
Stops conversion operation
Enables conversion operation
Stops A/D voltage comparator operation
Enables A/D voltage comparator operation
6
0
Stop status (DC power consumption path does not exist)
Conversion waiting mode (only A/D voltage comparator consumes power)
Setting prohibited
Conversion mode (A/D voltage comparator: enables operation)
Table 10-2. Settings of ADCS and ADCE
Note
A/D voltage comparator : enables operation
FR2
CHAPTER 10 A/D CONVERTER
Conversion
operation
User’s Manual U17854EJ9V0UD
5
Note 1
R/W
A/D voltage comparator operation control
FR1
A/D conversion operation control
4
Note 1
Conversion
A/D Conversion Operation
waiting
FR0
3
Note 1
Conversion
operation
LV1
2
Note 1
Conversion
stopped
LV0
Note 2
1
Note 1
ADCE
<0>
μ
s or more has
μ
s from
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