UPD78F1143AGK-GAJ-AX Renesas Electronics America, UPD78F1143AGK-GAJ-AX Datasheet - Page 484
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UPD78F1143AGK-GAJ-AX
Manufacturer Part Number
UPD78F1143AGK-GAJ-AX
Description
MCU 16BIT 78K0R/KX3 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet
1.UPD78F1142AGA-HAB-AX.pdf
(880 pages)
Specifications of UPD78F1143AGK-GAJ-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
96KB (96K x 8)
Program Memory Type
FLASH
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1143AGK-GAJ-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Remarks 1. Bit 1 (STT0) becomes 0 when it is read after data setting.
Note The signal of this bit is invalid while IICE0 is 0.
Cautions concerning set timing
• For master reception:
• For master transmission: A start condition cannot be generated normally during the acknowledge period. Set to 1
• Cannot be set to 1 at the same time as SPT0.
• Setting STT0 to 1 and then setting it again before it is cleared to 0 is prohibited.
Condition for clearing (STT0 = 0)
• Cleared by setting SST0 to 1 while communication
• Cleared by loss in arbitration
• Cleared after start condition is generated by master
• Cleared by LREL0 = 1 (exit from communications)
• When IICE0 = 0 (operation stop)
• Reset
STT0
device
reservation is prohibited.
0
1
Note
2. IICRSV: Bit 0 of IIC flag register (IICF0)
Do not generate a start condition.
When bus is released (in standby state, when IICBSY = 0):
When a third party is communicating:
In the wait state (when master device):
Generate a start condition (for starting as master). When the SCL0 line is high level, the SDA0 line is
Generates a restart condition after releasing the wait.
changed from high level to low level and then the start condition is generated. Next, after the rated
amount of time has elapsed, SCL0 is changed to low level (wait state).
• When communication reservation function is enabled (IICRSV = 0)
• When communication reservation function is disabled (IICRSV = 1)
STCF: Bit 7 of IIC flag register (IICF0)
Figure 12-6. Format of IIC Control Register 0 (IICC0) (3/4)
Functions as the start condition reservation flag. When set to 1, automatically generates a start
condition after the bus is released.
STCF is set to 1 and STT0 is cleared to 0. No start condition is generated.
Cannot be set to 1 during transfer. Can be set to 1 only in the waiting period when
ACKE0 has been cleared to 0 and slave has been notified of final reception.
during the wait period that follows output of the ninth clock.
CHAPTER 12 SERIAL INTERFACE IIC0
User’s Manual U17854EJ9V0UD
Start condition trigger
Condition for setting (STT0 = 1)
• Set by instruction
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