UPD78F1143AGK-GAJ-AX Renesas Electronics America, UPD78F1143AGK-GAJ-AX Datasheet - Page 604
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UPD78F1143AGK-GAJ-AX
Manufacturer Part Number
UPD78F1143AGK-GAJ-AX
Description
MCU 16BIT 78K0R/KX3 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet
1.UPD78F1142AGA-HAB-AX.pdf
(880 pages)
Specifications of UPD78F1143AGK-GAJ-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
96KB (96K x 8)
Program Memory Type
FLASH
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1143AGK-GAJ-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 604 of 880
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(2) Oscillation stabilization time select register (OSTS)
602
Cautions 1. To set the STOP mode when the X1 clock is used as the CPU clock, set OSTS before
Remark f
This register is used to select the X1 clock oscillation stabilization wait time when the STOP mode is released.
When the X1 clock is selected as the CPU clock, the operation waits for the time set using OSTS after the STOP
mode is released.
When the internal high-speed oscillation clock is selected as the CPU clock, confirm with OSTC that the desired
oscillation stabilization time has elapsed after the STOP mode is released. The oscillation stabilization time can
be checked up to the time set using OSTC.
OSTS can be set by an 8-bit memory manipulation instruction.
Reset signal generation sets this register to 07H.
Address: FFFA3H
Symbol
OSTS
2. Setting the oscillation stabilization time to 20
3. Before changing the setting of the OSTS register, confirm that the count operation of the
4. Do not change the value of the OSTS register during the X1 clock oscillation stabilization
5. The oscillation stabilization time counter counts up to the oscillation stabilization time set
6. The X1 clock oscillation stabilization wait time does not include the time until clock
X
: X1 clock oscillation frequency
Figure 17-2. Format of Oscillation Stabilization Time Select Register (OSTS)
executing the STOP instruction.
OSTC register is completed.
time.
by OSTS. If the STOP mode is entered and then released while the internal high-speed
oscillation clock is being used as the CPU clock, set the oscillation stabilization time as
follows.
Note, therefore, that only the status up to the oscillation stabilization time set by OSTS is
set to OSTC after STOP mode is released.
oscillation starts (“a” below).
OSTS2
• Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time set by OSTS
7
0
0
0
0
0
1
1
1
1
After reset: 07H
OSTS1
6
0
0
0
1
1
0
0
1
1
X1 pin voltage
waveform
CHAPTER 17 STANDBY FUNCTION
R/W
OSTS0
User’s Manual U17854EJ9V0UD
5
0
0
1
0
1
0
1
0
1
STOP mode release
2
2
2
2
2
2
2
2
8
9
10
11
13
15
17
18
/f
/f
/f
/f
/f
/f
/f
/f
X
X
X
X
X
X
X
X
4
0
a
Oscillation stabilization time selection
μ
s or less is prohibited.
3
0
25.6
51.2
102.4
204.8
819.2
3.27 ms
13.11 ms
26.21 ms
f
X
μ
μ
μ
μ
μ
= 10 MHz
s
s
OSTS2
s
s
s
2
OSTS1
Setting prohibited
25.6
51.2
102.4
409.6
1.64 ms
6.55 ms
13.11 ms
1
f
X
μ
μ
μ
μ
= 20 MHz
s
s
s
s
OSTS0
0
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