UPD78F1143AGK-GAJ-AX Renesas Electronics America, UPD78F1143AGK-GAJ-AX Datasheet - Page 450
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UPD78F1143AGK-GAJ-AX
Manufacturer Part Number
UPD78F1143AGK-GAJ-AX
Description
MCU 16BIT 78K0R/KX3 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet
1.UPD78F1142AGA-HAB-AX.pdf
(880 pages)
Specifications of UPD78F1143AGK-GAJ-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
96KB (96K x 8)
Program Memory Type
FLASH
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1143AGK-GAJ-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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(3) Permissible baud rate range for reception
Permissible maximum
The permissible baud rate range for reception during UART (UART0, UART1, UART3) communication can be
calculated by the following expression. Make sure that the baud rate at the transmission side is within the
permissible baud rate range at the reception side.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 1, 3)
Permissible minimum
As shown in Figure 11-90, the timing of latching receive data is determined by the division ratio set by bits 15
to 9 of the serial data register mn (SDRmn) after the start bit is detected. If the last data (stop bit) is received
before this latch timing, the data can be correctly received.
(Minimum receivable baud rate) =
(Maximum receivable baud rate) =
Brate: Calculated baud rate value at the reception side (See 11.6.5 (1) Baud rate calculation expression.)
k:
Nfr:
Data frame length
Figure 11-90. Permissible Baud Rate Range for Reception (1 Data Frame Length = 11 Bits)
data frame length
data frame length
SDRmn[15:9] + 1
1 data frame length [bits]
= (Start bit) + (Data length) + (Parity bit) + (Stop bit)
of SAU
timing
Latch
Start
Start
bit
Start
bit
bit
CHAPTER 11 SERIAL ARRAY UNIT
User’s Manual U17854EJ9V0UD
Bit 0
Bit 0
2 × k × Nfr − k + 2
2 × k × Nfr − k − 2
2 × k × (Nfr − 1)
FL
Bit 0
2 × k × Nfr
Bit 1
Bit 1
Bit 1
1 data frame (11 × FL)
(11 × FL) min.
(11 × FL) max.
× Brate
× Brate
Bit 7
Bit 7
Bit 7
Parity
bit
Parity
bit
Parity
bit
Stop
bit
Stop
bit
Stop
bit
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