UPD78F1143AGK-GAJ-AX Renesas Electronics America, UPD78F1143AGK-GAJ-AX Datasheet - Page 398
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UPD78F1143AGK-GAJ-AX
Manufacturer Part Number
UPD78F1143AGK-GAJ-AX
Description
MCU 16BIT 78K0R/KX3 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet
1.UPD78F1142AGA-HAB-AX.pdf
(880 pages)
Specifications of UPD78F1143AGK-GAJ-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
96KB (96K x 8)
Program Memory Type
FLASH
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1143AGK-GAJ-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Figure 11-51. Procedure for Resuming Slave Transmission
Manipulating target for communication
Changing setting of SOE0 register
Changing setting of SPS0 register
Changing setting of SOE0 register
Changing setting of SMR0n register
Changing setting of SCR0n register
Changing setting of SO0 register
Starting target for communication
Starting setting for resumption
Starting communication
Writing to SS0 register
Clearing error flag
Port manipulation
Port manipulation
CHAPTER 11 SERIAL ARRAY UNIT
User’s Manual U17854EJ9V0UD
Stop the target for communication or wait
until the target completes its operation.
Disable data output of the target channel
by setting a port register and a port
mode register.
Change the setting if an incorrect division
ratio of the operation clock is set.
Change the setting if the setting of the
SMR0n register is incorrect.
Change the setting if the setting of the
SCR0n register is incorrect.
Cleared by using SIR0n register if FEF,
PEF, or OVF flag remains set.
Manipulate the SO0n bit and set an
initial output level.
Set the SOE0 register and enable data
output of the target channel.
Enable data output of the target channel
by setting a port register and a port
mode register.
SE0n = 1 when the SS0n bit of the
target channel is set to 1.
Sets transmit data to the SIOp register (bits
7 to 0 of the SDR0n register) and wait for a
clock from the master.
Starts the target for communication.
Set the SOE0 register and stop data
output of the target channel.
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