UPD78F1143AGK-GAJ-AX Renesas Electronics America, UPD78F1143AGK-GAJ-AX Datasheet - Page 704
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UPD78F1143AGK-GAJ-AX
Manufacturer Part Number
UPD78F1143AGK-GAJ-AX
Description
MCU 16BIT 78K0R/KX3 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet
1.UPD78F1142AGA-HAB-AX.pdf
(880 pages)
Specifications of UPD78F1143AGK-GAJ-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
96KB (96K x 8)
Program Memory Type
FLASH
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1143AGK-GAJ-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Notes 1.
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
702
Instruction
Call/
return
Group
2.
2. This number of clocks is for when the program is in the internal ROM (flash memory) area. When
Mnemonic
CALL
CALLT
BRK
RET
RETI
RETB
When the internal RAM area, SFR area, or extended SFR area is accessed, or for an instruction with no
data access.
When the program memory area is accessed.
register (CKC).
fetching an instruction from the internal RAM area, the number of clocks is twice the number of clocks
plus 3, maximum.
rp
$!addr20
!addr16
!!addr20
[addr5]
Operands
−
−
−
−
Table 26-5. Operation List (15/17)
CHAPTER 26 INSTRUCTION SET
Bytes
2
3
3
4
2
2
1
2
2
User’s Manual U17854EJ9V0UD
Note 1 Note 2
3
3
3
3
5
5
6
6
6
Clocks
−
−
−
−
−
−
−
−
−
(SP − 2) ← (PC + 2)
(SP − 4) ← (PC + 2)
SP ← SP − 4
(SP − 2) ← (PC + 3)
(SP − 4) ← (PC + 3)
jdisp16,
SP ← SP − 4
(SP − 2) ← (PC + 3)
(SP − 4) ← (PC + 3)
SP ← SP − 4
(SP − 2) ← (PC + 4)
(SP − 4) ← (PC + 4)
SP ← SP − 4
(SP − 2) ← (PC + 2)
(SP − 4) ← (PC + 2)
PC
PC
SP ← SP − 4
(SP − 1) ← PSW, (SP − 2) ← (PC + 2)
(SP − 3) ← (PC + 2)
PC
PC
SP ← SP − 4, IE ← 0
PC
PC
PC
PC
SP ← SP + 4
PC
PC
SP ← SP + 4
H
L
S
H
L
S
L
S
L
S
← (SP + 2), PSW ← (SP + 3),
← (0000, addr5),
← (SP), PC
← (SP), PC
← (SP), PC
← (0000, addr5 + 1),
← 0000,
← (0007FH), PC
← (SP + 2), SP ← SP + 4
← (SP + 2), PSW ← (SP + 3),
CLK
) selected by the system clock control
H
H
Operation
H
← (SP + 1),
← (SP + 1),
← (SP + 1),
S
L
S
L
S
L
S
L
S
L
H
, PC ← CS, rp,
, PC ← PC + 3 +
, PC ← 0000, addr16,
, PC ← addr20,
, (SP − 3) ← (PC + 2)
, (SP − 3) ← (PC + 3)
, (SP − 3) ← (PC + 3)
, (SP − 3) ← (PC + 4)
, (SP − 3) ← (PC + 2)
, (SP − 4) ← (PC + 2)
, PC
L
← (0007EH),
S
← 0000,
S
,
H
H
H
H
H
L
,
,
,
,
,
,
R
R
Z AC CY
Flag
R
R
R
R
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