UPD78F1143AGK-GAJ-AX Renesas Electronics America, UPD78F1143AGK-GAJ-AX Datasheet - Page 607
![no-image](/images/manufacturer_photos/0/5/560/renesas_electronics_america_sml.jpg)
UPD78F1143AGK-GAJ-AX
Manufacturer Part Number
UPD78F1143AGK-GAJ-AX
Description
MCU 16BIT 78K0R/KX3 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet
1.UPD78F1142AGA-HAB-AX.pdf
(880 pages)
Specifications of UPD78F1143AGK-GAJ-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
96KB (96K x 8)
Program Memory Type
FLASH
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1143AGK-GAJ-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 607 of 880
- Download datasheet (6Mb)
Remark f
Item
System clock
CPU
Flash memory
RAM
Port (latch)
Timer array unit (TAU)
Real-time counter (RTC)
Watchdog timer
Clock output/buzzer output
A/D converter
Serial array unit (SAU)
Serial interface (IIC0)
Multiplier
DMA controller
Power-on-clear function
Low-voltage detection function
External interrupt
Key interrupt function
Main system clock
Subsystem clock
f
IL
f
f
f
f
IH
X
EX
XT
IL
HALT Mode Setting
:
:
:
: XT1 clock
: External main system clock
Internal high-speed oscillation clock
X1 clock
Internal low-speed oscillation clock
f
f
f
f
IH
X
EX
XT
Clock supply to the CPU is stopped
Status before HALT mode was set is retained
Operates or stops by external clock input
Operation continues (cannot be stopped)
Set by bits 0 (WDSTBYON) and 4 (WTON) of option byte (000C0H)
• WTON = 0: Stops
• WTON = 1 and WDSTBYON = 1: Oscillates
• WTON = 1 and WDSTBYON = 0: Stops
Operation stopped
Operable in low-current consumption mode
Operation stopped. However, status before HALT mode was set is retained at voltage higher
than POC detection voltage.
Status before HALT mode was set is retained
Operable
Set by bits 0 (WDSTBYON) and 4 (WTON) of option byte (000C0H)
• WTON = 0: Stops
• WTON = 1 and WDSTBYON = 1: Operates
• WTON = 1 and WDSTBYON = 0: Stops
Operable
Cannot operate
Operable
Cannot operate
Operation stopped
Operable
Table 17-1. Operating Statuses in HALT Mode (2/2)
When HALT Instruction Is Executed While CPU Is Operating on Subsystem Clock
CHAPTER 17 STANDBY FUNCTION
User’s Manual U17854EJ9V0UD
When CPU Is Operating on XT1 Clock (f
XT
)
605
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