UPD78F1143AGK-GAJ-AX Renesas Electronics America, UPD78F1143AGK-GAJ-AX Datasheet - Page 481
![no-image](/images/manufacturer_photos/0/5/560/renesas_electronics_america_sml.jpg)
UPD78F1143AGK-GAJ-AX
Manufacturer Part Number
UPD78F1143AGK-GAJ-AX
Description
MCU 16BIT 78K0R/KX3 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet
1.UPD78F1142AGA-HAB-AX.pdf
(880 pages)
Specifications of UPD78F1143AGK-GAJ-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
96KB (96K x 8)
Program Memory Type
FLASH
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1143AGK-GAJ-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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12.3 Registers to Controlling Serial Interface IIC0
Address: F00F0H
Serial interface IIC0 is controlled by the following eight registers.
(1) Peripheral enable register 0 (PER0)
(2) IIC control register 0 (IICC0)
Symbol
PER0
• Peripheral enable register 0 (PER0)
• IIC control register 0 (IICC0)
• IIC flag register 0 (IICF0)
• IIC status register 0 (IICS0)
• IIC clock select register 0 (IICCL0)
• IIC function expansion register 0 (IICX0)
• Port mode register 6 (PM6)
• Port register 6 (P6)
PER0 is used to enable or disable use of each peripheral hardware macro. Clock supply to a hardware macro
that is not used is stopped in order to reduce the power consumption and noise.
When serial interface IIC0 is used, be sure to set bit 4 (IIC0EN) of this register to 1.
PER0 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Cautions 1. When setting serial interface IIC0, be sure to set IIC0EN to 1 first. If IIC0EN = 0, writing to a
This register is used to enable/stop I
IICC0 can be set by a 1-bit or 8-bit memory manipulation instruction. However, set the SPIE0, WTIM0, and
ACKE0 bits while IICE0 bit = 0 or during the wait period. These bits can be set at the same time when the
IICE0 bit is set from “0” to “1”.
Reset signal generation clears this register to 00H.
RTCEN
IIC0EN
2. Be sure to clear bits 1 and 6 of PER0 register to 0.
<7>
0
1
After reset: 00H
control register of serial interface IIC0 is ignored, and, even if the register is read, only the
default value is read (except for port mode register 6 (PM6) and port register 6 (P6)).
Stops supply of input clock.
• SFR used by serial interface IIC0 cannot be written.
• Serial interface IIC0 is in the reset status.
Supplies input clock.
• SFR used by serial interface IIC0 can be read/written.
Figure 12-5. Format of Peripheral Enable Register 0 (PER0)
6
0
R/W
CHAPTER 12 SERIAL INTERFACE IIC0
ADCEN
2
<5>
C operations, set wait timing, and set other I
User’s Manual U17854EJ9V0UD
Control of serial interface IIC0 input clock
IIC0EN
<4>
SAU1EN
<3>
SAU0EN
<2>
2
C operations.
1
0
TAU0EN
<0>
479
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