UPD78F1143AGK-GAJ-AX Renesas Electronics America, UPD78F1143AGK-GAJ-AX Datasheet - Page 409
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UPD78F1143AGK-GAJ-AX
Manufacturer Part Number
UPD78F1143AGK-GAJ-AX
Description
MCU 16BIT 78K0R/KX3 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet
1.UPD78F1142AGA-HAB-AX.pdf
(880 pages)
Specifications of UPD78F1143AGK-GAJ-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
96KB (96K x 8)
Program Memory Type
FLASH
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1143AGK-GAJ-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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11.5.6 Slave transmission/reception
transfer clock being input from another device.
Target channel
Pins used
Interrupt
Error detection flag
Transfer data length
Transfer rate
Data phase
Clock phase
Data direction
Slave transmission/reception is that the 78K0R/KE3 transmits/receives data to/from another device in the state of a
Notes 1. Because the external serial clock input to pins SCK00 and SCK10 is sampled internally and used, the
Remarks 1. f
3-Wire Serial I/O
2. Use this operation within a range that satisfies the conditions above and the AC characteristics in the
electrical specifications (see CHAPTER 27
PRODUCTS) and CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)).
fastest transfer rate is f
2. n: Channel number (n = 0 to 2)
MCK
: Operation clock (MCK) frequency of target channel
Channel 0 of SAU0
SCK00, SI00, SO00
INTCSI00
Transfer end interrupt (in single-transfer mode) or buffer empty interrupt (in continuous transfer mode)
can be selected.
Overrun error detection flag (OVF0n) only
7 or 8 bits
Max. f
Selectable by DAP0n bit
• DAP0n = 0: Data output starts from the start of the operation of the serial clock.
• DAP0n = 1: Data output starts half a clock before the start of the serial clock operation.
Selectable by CKP0n bit
• CKP0n = 0: Forward
• CKP0n = 1: Reverse
MSB or LSB first
MCK
/6 [Hz]
MCK
Notes 1, 2
/6 [Hz].
CHAPTER 11 SERIAL ARRAY UNIT
CSI00
User’s Manual U17854EJ9V0UD
ELECTRICAL SPECIFICATIONS (STANDARD
Channel 2 of SAU0
SCK10, SI10, SO10
INTCSI10
CSI10
407
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