SAK-TC1736-128F80HL AA Infineon Technologies, SAK-TC1736-128F80HL AA Datasheet - Page 51

• Manufacturer Part Number: SAK-TC1736-128F80HL AA
• Description: IC MCU 32BIT 1MB FLASH 144LQFP
• Manufacturer: Infineon Technologies
• Series: TC17xxr

Specifications of SAK-TC1736-128F80HL AA

• Core Processor: TriCore
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: ASC, CAN, MLI, MSC, SSC
• Peripherals: DMA, POR, WDT
• Number Of I /o: 70
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.42 V ~ 1.58 V
• Data Converters: A/D 24x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-LFQFP
• Packages: PG-LQFP-144
• Max Clock Frequency: 80.0 MHz
• Sram (incl. Cache): 48.0 KByte
• Can Nodes: 2
• A / D Input Lines (incl. Fadc): 24
• Program Memory: 1.0 MB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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Features of the Digital Part of each ADC Kernel
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2.5.8
General Features
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Data Sheet
Input multiplexer width of 16 possible analog input channels (not all of them are
necessarily available on pins)
V
Programmable sample time (in periods of
Wide range of accepted analog clock frequencies
Multiplexer test mode (channel 7 input can be connected to ground via a resistor for
test purposes during run time by specific control bit)
Power saving mechanisms
Independent result registers (16 independent registers)
5 conversion request sources (e.g. for external events, auto-scan, programmable
sequence, etc.)
Synchronization of the ADC kernels for concurrent conversion starts
Control an external analog multiplexer, respecting the additional set up time
Programmable sampling times for different channels
Possibility to cancel running conversions on demand with automatic restart
Flexible interrupt generation (possibility of DMA support)
Limit checking to reduce interrupt load
Programmable data reduction filter by adding conversion results
Support of conversion data FIFO
Support of suspend and power down modes
Individually programmable reference selection for each channel (with exception of
dedicated channels always referring to
Extreme fast conversion, 21 cycles of
10-bit A/D conversion (higher resolution can be achieved by averaging of
consecutive conversions in digital data reduction filter)
Successive approximation conversion method
Two differential input channels with impedance control overlaid with ADC1 inputs
Each differential input channel can also be used as single-ended input
Offset and gain calibration support for each channel
Programmable gain of 1, 2, 4, or 8 for each channel
Free-running (Channel Timers) or triggered conversion modes
Trigger and gating control for external signals
Built-in Channel Timers for internal triggering
Channel timer request periods independently selectable for each channel
Selectable, programmable digital anti-aliasing and data reduction filter block with four
independent filter units
AREF
and 1 alternative reference input at channel 0
Fast Analog to Digital Converter (FADC)
f
FADC
47
V
AREF
f
ADCI
clock (262.5 ns @
)
f
ADCI
f
FADC
= 80 MHz)
Introduction
V1.1, 2009-08
TC1736