C8051F023R Silicon Laboratories Inc, C8051F023R Datasheet - Page 12

• Manufacturer Part Number: C8051F023R
• Description: IC 8051 MCU 64K FLASH 64TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F02xr

Specifications of C8051F023R

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 32
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x8b, 8x10b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: 336-1035-2

C8051F020/1/2/3
16. EXTERNAL DATA MEMORY INTERFACE AND ON-CHIP XRAM.......................145
17. PORT INPUT/OUTPUT .....................................................................................................161
12
Table 15.1. FLASH Electrical Characteristics .....................................................................140
Figure 15.1. FLASH Program Memory Map and Security Bytes .........................................141
Figure 15.2. FLACL: FLASH Access Limit .........................................................................142
Figure 15.3. FLSCL: FLASH Memory Control ....................................................................143
Figure 15.4. PSCTL: Program Store Read/Write Control .....................................................144
Figure 16.1. EMI0CN: External Memory Interface Control .................................................147
Figure 16.2. EMI0CF: External Memory Configuration .......................................................147
Figure 16.3. Multiplexed Configuration Example.................................................................148
Figure 16.4. Non-multiplexed Configuration Example .........................................................149
Figure 16.5. EMIF Operating Modes.....................................................................................150
Figure 16.6. EMI0TC: External Memory Timing Control ....................................................152
Figure 16.7. Non-multiplexed 16-bit MOVX Timing ...........................................................153
Figure 16.8. Non-multiplexed 8-bit MOVX without Bank Select Timing............................154
Figure 16.9. Non-multiplexed 8-bit MOVX with Bank Select Timing.................................155
Figure 16.10. Multiplexed 16-bit MOVX Timing .................................................................156
Figure 16.11. Multiplexed 8-bit MOVX without Bank Select Timing .................................157
Figure 16.12. Multiplexed 8-bit MOVX with Bank Select Timing.......................................158
Table 16.1. AC Parameters for External Memory Interface.................................................159
Figure 17.1. Port I/O Cell Block Diagram.............................................................................161
Table 17.1. Port I/O DC Electrical Characteristics ..............................................................161
Figure 17.2. Lower Port I/O Functional Block Diagram .......................................................162
Figure 17.3. Priority Crossbar Decode Table ........................................................................163
Figure 17.4. Priority Crossbar Decode Table ........................................................................166
Figure 17.5. Priority Crossbar Decode Table ........................................................................167
Figure 17.6. Crossbar Example: ............................................................................................169
Figure 17.7. XBR0: Port I/O Crossbar Register 0 .................................................................170
Figure 17.8. XBR1: Port I/O Crossbar Register 1 .................................................................171
Figure 17.9. XBR2: Port I/O Crossbar Register 2 .................................................................172
Figure 17.10. P0: Port0 Data Register ...................................................................................173
Figure 17.11. P0MDOUT: Port0 Output Mode Register.......................................................173
Figure 17.12. P1: Port1 Data Register ...................................................................................174
Figure 17.13. P1MDIN: Port1 Input Mode Register .............................................................174
Figure 17.14. P1MDOUT: Port1 Output Mode Register.......................................................175
Figure 17.15. P2: Port2 Data Register ...................................................................................175
Figure 17.16. P2MDOUT: Port2 Output Mode Register.......................................................175
Figure 17.17. P3: Port3 Data Register ...................................................................................176
Figure 17.18. P3MDOUT: Port3 Output Mode Register.......................................................176
Figure 17.19. P3IF: Port3 Interrupt Flag Register .................................................................177
Figure 17.20. P74OUT: Ports 7 - 4 Output Mode Register ...................................................179
Figure 17.21. P4: Port4 Data Register ...................................................................................180
Figure 17.22. P5: Port5 Data Register ...................................................................................180
Figure 17.23. P6: Port6 Data Register ...................................................................................181
Figure 17.24. P7: Port7 Data Register ...................................................................................181
Rev. 1.4