C8051F023R Silicon Laboratories Inc, C8051F023R Datasheet - Page 218

IC 8051 MCU 64K FLASH 64TQFP

C8051F023R

Manufacturer Part Number
C8051F023R
Description
IC 8051 MCU 64K FLASH 64TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F02xr
Datasheets

Specifications of C8051F023R

Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
32
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x8b, 8x10b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
336-1035-2
C8051F020/1/2/3
21.1.3. Mode 2: 9-Bit UART, Fixed Baud Rate
Mode 2 provides asynchronous, full-duplex communication using a total of eleven bits per data byte: a start bit, 8 data
bits (LSB first), a programmable ninth data bit, and a stop bit. Mode 2 supports multiprocessor communications and
hardware address recognition (see
the ninth data bit is determined by the value in TB81 (SCON1.3). It can be assigned the value of the parity flag P in
the PSW or used in multiprocessor communications. On receive, the ninth data bit goes into RB81 (SCON1.2) and
the stop bit is ignored.
Data transmission begins when an instruction writes a data byte to the SBUF1 register. The TI1 Transmit Interrupt
Flag (SCON1.1) is set at the end of the transmission (the beginning of the stop-bit time). Data reception can begin
any time after the REN1 Receive Enable bit (SCON1.4) is set to logic 1. After the stop bit is received, the data byte
will be loaded into the SBUF1 receive register if RI1 is logic 0 and one of the following requirements are met:
If the above conditions are satisfied, the eight bits of data are stored in SBUF1, the ninth bit is stored in RB81 and the
RI1 flag is set. If these conditions are not met, SBUF1 and RB81 will not be loaded and the RI1 flag will not be set.
An interrupt will occur if enabled when either TI1 or RI1 is set.
The baud rate in Mode 2 is either SYSCLK / 32 or SYSCLK / 64, depending on the value of the SMOD1 bit in regis-
ter PCON.
218
SPACE
MARK
BIT TIMES
BIT SAMPLING
1.
2.
SM21 is logic 0
SM21 is logic 1, the received 9th bit is logic 1, and the received address matches the UART1 address as
described in
START
BIT
Figure 21.5. UART Modes 2 and 3 Timing Diagram
Section
D0
21.2.
D1
Section “21.2. Multiprocessor Communications” on page
BaudRate
Equation 21.3. Mode 2 Baud Rate
D2
=
D3
2
Rev. 1.4
SMOD1
D4
SYSCLK
--------------------- -
D5
64
D6
D7
220). On transmit,
D8
STOP
BIT

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