C8051F023R Silicon Laboratories Inc, C8051F023R Datasheet - Page 265

IC 8051 MCU 64K FLASH 64TQFP

C8051F023R

Manufacturer Part Number
C8051F023R
Description
IC 8051 MCU 64K FLASH 64TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F02xr
Datasheets

Specifications of C8051F023R

Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
32
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x8b, 8x10b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
336-1035-2
24.
Each MCU has an on-chip JTAG interface and logic to support boundary scan for production and in-system testing,
Flash read/write operations, and non-intrusive in-circuit debug. The JTAG interface is fully compliant with the IEEE
1149.1 specification. Refer to this specification for detailed descriptions of the Test Interface and Boundary-Scan
Architecture. Access of the JTAG Instruction Register (IR) and Data Registers (DR) are as described in the Test
Access Port and Operation of the IEEE 1149.1 specification.
The JTAG interface is accessed via four dedicated pins on the MCU: TCK, TMS, TDI, and TDO.
Through the 16-bit JTAG Instruction Register (IR), any of the seven instructions shown in Figure 24.1 can be com-
manded. There are three DR’s associated with JTAG Boundary-Scan, and four associated with Flash read/write oper-
ations on the MCU.
Bit15
IR Value
0xFFFF
0x0000
0x0002
0x0004
0x0082
0x0083
0x0084
JTAG (IEEE 1149.1)
Flash Address
Flash Control
PRELOAD
Instruction
SAMPLE/
Flash Data
EXTEST
IDCODE
BYPASS
Figure 24.1. IR: JTAG Instruction Register
Selects the Boundary Data Register for control and observability of all device pins
Selects FLASHADR Register which holds the address of all Flash read, write, and
Selects FLASHCON Register to control how the interface logic responds to reads
Selects the Boundary Data Register for observability and presetting the scan-path
Selects FLASHDAT Register for reads and writes to the Flash memory
and writes to the FLASHDAT Register
Selects Bypass Data Register
Rev. 1.4
Selects device ID Register
erase operations
Description
latches
C8051F020/1/2/3
Bit0
Reset Value
0x0000
265

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