C8051F023R Silicon Laboratories Inc, C8051F023R Datasheet - Page 194

• Manufacturer Part Number: C8051F023R
• Description: IC 8051 MCU 64K FLASH 64TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F02xr

Specifications of C8051F023R

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 32
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x8b, 8x10b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: 336-1035-2

C8051F020/1/2/3
18.4.5. Status Register
The SMB0STA Status register holds an 8-bit status code indicating the current state of the SMBus0 interface. There
are 28 possible SMBus0 states, each with a corresponding unique status code. The five most significant bits of the
status code vary while the three least-significant bits of a valid status code are fixed at zero when SI = ‘1’. Therefore,
all possible status codes are multiples of eight. This facilitates the use of status codes in software as an index used to
branch to appropriate service routines (allowing 8 bytes of code to service the state or jump to a more extensive ser-
vice routine).
For the purposes of user software, the contents of the SMB0STA register is only defined when the SI flag is logic 1.
Software should never write to the SMB0STA register; doing so will yield indeterminate results. The 28 SMBus0
states, along with their corresponding status codes, are given in Table 1.1.
194
Bits7-3:
Bits2-0:
STA7
R/W
Bit7
STA7-STA3: SMBus0 Status Code.
These bits contain the SMBus0 Status Code. There are 28 possible status codes; each status code cor-
responds to a single SMBus state. A valid status code is present in SMB0STA when the SI flag
(SMB0CN.3) is set to logic 1. The content of SMB0STA is not defined when the SI flag is logic 0.
Writing to the SMB0STA register at any time will yield indeterminate results.
STA2-STA0: The three least significant bits of SMB0STA are always read as logic 0 when the SI flag
is logic 1.
STA6
R/W
Bit6
Figure 18.12. SMB0STA: SMBus0 Status Register
STA5
R/W
Bit5
STA4
R/W
Bit4
Rev. 1.4
STA3
R/W
Bit3
STA2
R/W
Bit2
STA1
R/W
Bit1
STA0
R/W
Bit0
SFR Address:
00000000
Reset Value
0xC1