C8051F023R Silicon Laboratories Inc, C8051F023R Datasheet - Page 188

IC 8051 MCU 64K FLASH 64TQFP

C8051F023R

Manufacturer Part Number
C8051F023R
Description
IC 8051 MCU 64K FLASH 64TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F02xr
Datasheets

Specifications of C8051F023R

Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
32
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x8b, 8x10b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
336-1035-2
C8051F020/1/2/3
18.3.3. Slave Transmitter Mode
Serial data is transmitted on SDA while the serial clock is received on SCL. The SMBus0 interface receives a START
followed by data byte containing the slave address and direction bit. If the received slave address matches the address
held in register SMB0ADR, the SMBus0 interface generates an ACK. SMBus0 will also ACK if the general call
address (0x00) is received and the General Call Address Enable bit (SMB0ADR.0) is set to logic 1. In this case the
data direction bit (R/W) will be logic 1 to indicate a "READ" operation. The SMBus0 interface receives the clock on
SCL and transmits one or more bytes of serial data, waiting for an ACK from the master after each byte. SMBus0
exits slave mode after receiving a STOP condition from the master.
18.3.4. Slave Receiver Mode
Serial data is received on SDA while the serial clock is received on SCL. The SMBus0 interface receives a START
followed by data byte containing the slave address and direction bit. If the received slave address matches the address
held in register SMB0ADR, the interface generates an ACK. SMBus0 will also ACK if the general call address
(0x00) is received and the General Call Address Enable bit (SMB0ADR.0) is set to logic 1. In this case the data direc-
tion bit (R/W) will be logic 0 to indicate a "WRITE" operation. The SMBus0 interface receives one or more bytes of
serial data; after each byte is received, the interface transmits an ACK or NACK depending on the state of the AA bit
in SMB0CN. SMBus0 exits Slave Receiver Mode after receiving a STOP condition from the master.
188
S
S
Received by SMBus
Interface
Transmitted by
SMBus Interface
Received by SMBus
Interface
Transmitted by
SMBus Interface
SLA
SLA
Figure 18.6. Typical Slave Transmitter Sequence
Figure 18.7. Typical Slave Receiver Sequence
Interrupt
W
R
Interrupt
A
A
Data Byte
Data Byte
Rev. 1.4
Interrupt
Interrupt
A
A
S = START
P = STOP
N = NACK
W = WRITE
SLA = Slave Address
S = START
P = STOP
A = ACK
R = READ
SLA = Slave Address
Data Byte
Data Byte
Interrupt
Interrupt
N
A
Interrupt
Interrupt
P
P

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