PIC17C756-16/L Microchip Technology, PIC17C756-16/L Datasheet - Page 113

• Manufacturer Part Number: PIC17C756-16/L
• Description: MICRO CTRL 16K MEMORY OTP 68PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 17Cr

Specifications of PIC17C756-16/L

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: OTP
• Ram Size: 902 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 68-PLCC
• For Use With: AC164308 - MODULE SKT FOR PM3 68PLCCDVA17XL681 - DEVICE ADAPTER FOR PIC17C752DM173001 - KIT DEVELOPMENT PICDEM17AC174007 - MODULE SKT PROMATEII 68PLCCAC164024 - ADAPTER PICSTART PLUS 68PLCC
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -

14.2
In this mode, the USART uses standard nonre-
turn-to-zero (NRZ) format (one start bit, eight or nine
data bits, and one stop bit). The most common data for-
mat is 8-bits. An on-chip dedicated 8-bit baud rate gen-
erator can be used to derive standard baud rate
frequencies from the oscillator. The USART’s transmit-
ter and receiver are functionally independent but use
the same data format and baud rate. The baud rate
generator produces a clock x64 of the bit shift rate. Par-
ity is not supported by the hardware, but can be imple-
mented in software (and stored as the ninth data bit).
Asynchronous mode is stopped during SLEEP.
The asynchronous mode is selected by clearing the
SYNC bit (TXSTA<4>).
The USART Asynchronous module consists of the fol-
lowing important elements:
• Baud Rate Generator
• Sampling Circuit
• Asynchronous Transmitter
• Asynchronous Receiver
14.2.1
The USART transmitter block diagram is shown in
Figure 14-3. The heart of the transmitter is the transmit
shift register (TSR). The shift register obtains its data
from the read/write transmit buffer (TXREG). TXREG is
loaded with data in software. The TSR is not loaded
until the stop bit has been transmitted from the previous
load. As soon as the stop bit is transmitted, the TSR is
loaded with new data from the TXREG (if available).
Once TXREG transfers the data to the TSR (occurs in
one T
TXREG is empty and an interrupt bit, TXIF, is set. This
interrupt can be enabled/disabled by setting/clearing
the TXIE bit. TXIF will be set regardless of TXIE and
cannot be reset in software. It will reset only when new
data is loaded into TXREG. While TXIF indicates the
status of the TXREG, the TRMT (TXSTA<1>) bit shows
the status of the TSR. TRMT is a read only bit which is
set when the TSR is empty. No interrupt logic is tied to
this bit, so the user has to poll this bit in order to deter-
mine if the TSR is empty.
1997 Microchip Technology Inc.
Note:
CY
USART Asynchronous Mode
USART ASYNCHRONOUS TRANSMITTER
at the end of the current BRG cycle), the
The TSR is not mapped in data memory,
so it is not available to the user.
Preliminary
Transmission
TXEN (TXSTA<5>) bit. The actual transmission will not
occur until TXREG has been loaded with data and the
baud rate generator (BRG) has produced a shift clock
(Figure 14-5). The transmission can also be started by
first loading TXREG and then setting TXEN. Normally
when transmission is first started, the TSR is empty, so
a transfer to TXREG will result in an immediate transfer
to TSR resulting in an empty TXREG. A back-to-back
transfer is thus possible (Figure 14-6). Clearing TXEN
during a transmission will cause the transmission to be
aborted. This will reset the transmitter and the TX/CK
pin will revert to hi-impedance.
In
TX9 (TXSTA<6>) bit should be set and the ninth bit
value should be written to TX9D (TXSTA<0>). The
ninth bit value must be written before writing the 8-bit
data to the TXREG. This is because a data write to
TXREG can result in an immediate transfer of the data
to the TSR (if the TSR is empty).
Steps to follow when setting up an Asynchronous
Transmission:
1.
2.
3.
4.
5.
6.
7.
Writing the transmit data to the TXREG, then enabling
the transmit (setting TXEN) allows transmission to start
sooner than doing these two events in the opposite
order.
Note:
Initialize the SPBRG register for the appropriate
baud rate.
Enable the asynchronous serial port by clearing
the SYNC bit and setting the SPEN bit.
If interrupts are desired, then set the TXIE bit.
If 9-bit transmission is desired, then set the TX9
bit.
Load data to the TXREG register.
If 9-bit transmission is selected, the ninth bit
should be loaded in TX9D.
Enable the transmission by setting TXEN (starts
transmission).
order
To terminate a transmission, either clear
the SPEN bit, or the TXEN bit. This will
reset the transmit logic, so that it will be in
the
re-enabled.
to
proper
is
select
enabled
state
9-bit
when
by
transmission,
DS30264A-page 113
setting
transmit
the
the
is