PIC17C756-16/L Microchip Technology, PIC17C756-16/L Datasheet - Page 291

• Manufacturer Part Number: PIC17C756-16/L
• Description: MICRO CTRL 16K MEMORY OTP 68PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 17Cr

Specifications of PIC17C756-16/L

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: OTP
• Ram Size: 902 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 68-PLCC
• For Use With: AC164308 - MODULE SKT FOR PM3 68PLCCDVA17XL681 - DEVICE ADAPTER FOR PIC17C752DM173001 - KIT DEVELOPMENT PICDEM17AC174007 - MODULE SKT PROMATEII 68PLCCAC164024 - ADAPTER PICSTART PLUS 68PLCC
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -

FIGURE F-19: SSPCON2: SYNC SERIAL PORT CONTROL REGISTER2 (ADDRESS 12h, BANK 6)
1997 Microchip Technology Inc.
bit 7:
bit 6:
bit 5:
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
GCEN
R/W-0
bit7
RSEN: Restart Condition Enabled bit (In I
SEN: Start Condition Enabled bit (In I
GCEN: General Call Enable bit (In I
1 = Enable interrupt when a general call address is received in the SSPSR.
0 = General call address disabled.
ACKSTAT: Acknowledge Status bit (In I
In master transmit mode:
1 = Acknowledge was not received from slave
0 = Acknowledge was received from slave
ACKDT: Acknowledge Data bit (In I
In master receive mode:
Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive.
1 = Not Acknowledge
0 = Acknowledge
ACKEN: Acknowledge Sequence Enable bit (In I
In master receive mode:
1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit AKD data bit. Automatically
0 = Acknowledge sequence idle
RCEN: Receive enable bit (In I
1 = Enables Receive mode for I
0 = Receive idle
PEN: Stop Condition Enable bit (In I
SCK release control
1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Stop condition idle
1 = Initiate Restart condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Restart condition idle.
1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Start condition idle.
Note: If the I
Note: If the I
Note: If the I
Note: If the I
Note: If the I
ACKSTAT ACKDT
R-0
cleared by hardware.
may not be written (or writes to the SSPBUF are disabled).
may not be written (or writes to the SSPBUF are disabled).
may not be written (or writes to the SSPBUF are disabled).
may not be written (or writes to the SSPBUF are disabled)
may not be written (or writes to the SSPBUF are disabled)
R/W-0
2
2
2
2
2
C module is not in the idle mode, this bit may not be set (no spooling), and the SSPBUF
C module is not in the idle mode, this bit may not be set (no spooling), and the SSPBUF
C module is not in the idle mode, this bit may not be set (no spooling), and the SSPBUF
C module is not in the idle mode, this bit may not be set (no spooling), and the SSPBUF
C module is not in the idle mode, this bit may not be set (no spooling), and the SSPBUF
ACKEN
R/W-0
2
2
C master mode only).
C
RCEN
R/W-0
2
2
2
2
C master mode only).
C slave mode only)
C master mode only)
C master mode only)
Preliminary
2
2
C master mode only)
C master mode only)
R/W-0
PEN
2
C master mode only).
R/W-0
RSEN
R/W-0
SEN
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
- n =Value at POR reset
Read as ‘0’
DS30264A-page 291