PIC17C756-16/L Microchip Technology, PIC17C756-16/L Datasheet - Page 58

• Manufacturer Part Number: PIC17C756-16/L
• Description: MICRO CTRL 16K MEMORY OTP 68PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 17Cr

Specifications of PIC17C756-16/L

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: OTP
• Ram Size: 902 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 68-PLCC
• For Use With: AC164308 - MODULE SKT FOR PM3 68PLCCDVA17XL681 - DEVICE ADAPTER FOR PIC17C752DM173001 - KIT DEVELOPMENT PICDEM17AC174007 - MODULE SKT PROMATEII 68PLCCAC164024 - ADAPTER PICSTART PLUS 68PLCC
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -

8.2
Table writes to external memory are always two-cycle
instructions. The second cycle writes the data to the
external memory location. The sequence of events for
an external memory write are the same for an internal
write.
FIGURE 8-5:
DS30264A-page 58
Note:
Note:
Table Writes to External Memory
If external write, and GLINTD = '1', and Enable bit = '1', then when '1'
The highest pending interrupt is cleared.
If an interrupt is pending or occurs during
the TABLWT, the two cycle table write
completes. The RA0/INT, TMR0, or
T0CKI interrupt flag is automatically
cleared or the pending peripheral inter-
rupt is acknowledged.
AD15:AD0
Instruction
executed
TABLWT WRITE TIMING (EXTERNAL MEMORY)
Instruction
fetched
ALE
WR
OE
Q1 Q2 Q3 Q4
'1'
INST (PC-1)
TABLWT
PC
Q1 Q2 Q3 Q4
TABLWT cycle1
Preliminary
INST (PC+1)
PC+1
8.2.2
The “i” operand of the TABLWT instruction can specify
that the value in the 16-bit TBLPTR register is auto-
matically
Example 8-1, the TBLPTR register is not automatically
incremented.
EXAMPLE 8-1:
CLRWDT
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
TLWT
MOVLW
TABLWT
Q1 Q2 Q3 Q4
Data write cycle
TABLWT cycle2
TBL
TABLE WRITE CODE
Flag bit, Do table write.
incremented
HIGH (TBL_ADDR) ; Load the Table
TBLPTRH
LOW (TBL_ADDR)
TBLPTRL
HIGH (DATA)
1, WREG
LOW (DATA)
0,0,WREG
Data out
TABLE WRITE
Q1 Q2 Q3 Q4
INST (PC+2)
INST (PC+1)
(for
1997 Microchip Technology Inc.
PC+2
the
; Clear WDT
;
;
;
; Load HI byte
;
; Load LO byte
;
;
;
;
address
in TABLATH
in TABLATH
and write to
program memory
(Ext. SRAM)
next
write). In