PIC17C756-16/L Microchip Technology, PIC17C756-16/L Datasheet - Page 281

• Manufacturer Part Number: PIC17C756-16/L
• Description: MICRO CTRL 16K MEMORY OTP 68PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 17Cr

Specifications of PIC17C756-16/L

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: OTP
• Ram Size: 902 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 68-PLCC
• For Use With: AC164308 - MODULE SKT FOR PM3 68PLCCDVA17XL681 - DEVICE ADAPTER FOR PIC17C752DM173001 - KIT DEVELOPMENT PICDEM17AC174007 - MODULE SKT PROMATEII 68PLCCAC164024 - ADAPTER PICSTART PLUS 68PLCC
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -

FIGURE F-9:
1997 Microchip Technology Inc.
bit7
bit 7:
bit 6:
bit 5:
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
R/W - 0 R/W - 0
SSPIF
SSPIF: Synchronous Serial Port (SSP) Interrupt Flag
1 = The SSP interrupt condition has occured, and must be cleared in software before returning from the
0 = An SSP interrupt condition has occurred.
BCLIF: Bus Collision Interrupt Flag
1 = A bus collision has occurred in the SSP, when configured for I
0 = No bus collision has occurred
ADIF: A/D Module Interrupt Flag
1 = An A/D conversion is complete
0 = An A/D conversion is not complete
Unimplemented: Read as '0'
CA4IF: Capture4 Interrupt Flag
1 = Capture event occurred on RE3/CAP4 pin
0 = Capture event did not occur on RE3/CAP4 pin
CA3IF: Capture3 Interrupt Flag
1 = Capture event occurred on RG4/CAP3 pin
0 = Capture event did not occur on RG4/CAP3 pin
TX2IF:USART2 Transmit Interrupt Flag
1 = USART2 Transmit buffer is empty
0 = USART2 Transmit buffer is full
RC2IF: USART2 Receive Interrupt Flag
1 = USART2 Receive buffer is full
0 = USART2 Receive buffer is empty
BCLIF
interrupt service routine. The conditions that will set this bit are:
SPI
I
I
2
2
C Slave / Master
C Master
PIR2 REGISTER (ADDRESS: 10h, BANK 4)
A transmission/reception has taken place.
A transmission/reception has taken place.
The initiated start condition was completed by the SSP module.
The initiated stop condition was completed by the SSP module.
The initiated restart condition was completed by the SSP module.
The initiated acknowledge condition was completed by the SSP module.
A start condition occurred while the SSP module was idle (Multimaster system).
A stop condition occurred while the SSP module was idle (Multimaster system).
R/W - 0
ADIF
U - 0
—
R/W - 0
CA4IF
Preliminary
R/W - 0
CA3IF
R/W - 1
TX2IF
R/W - 0
2
RC2IF
C master mode
bit0
R = Readable bit
W = Writable bit
-n = Value at POR reset
DS30264A-page 281