PIC17C756-16/L Microchip Technology, PIC17C756-16/L Datasheet - Page 196

• Manufacturer Part Number: PIC17C756-16/L
• Description: MICRO CTRL 16K MEMORY OTP 68PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 17Cr

Specifications of PIC17C756-16/L

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: OTP
• Ram Size: 902 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 68-PLCC
• For Use With: AC164308 - MODULE SKT FOR PM3 68PLCCDVA17XL681 - DEVICE ADAPTER FOR PIC17C752DM173001 - KIT DEVELOPMENT PICDEM17AC174007 - MODULE SKT PROMATEII 68PLCCAC164024 - ADAPTER PICSTART PLUS 68PLCC
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -

CPFSLT
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
If skip:
Example:
DS30264A-page 196
Before Instruction
After Instruction
operation
Decode
PC
W
If REG
PC
If REG
PC
Q1
Q1
No
register 'f'
operation
Compare f with WREG,
skip if f < WREG
[ label ] CPFSLT
0
(f) – WREG),
skip if (f) < (WREG)
(unsigned comparison)
None
Compares the contents of data memory
location 'f' to the contents of WREG by
performing an unsigned subtraction.
If the contents of 'f' are less than the
contents of WREG, then the fetched
instruction is discarded and an NOP is
executed instead making this a
two-cycle instruction.
1
1 (2)
HERE
NLESS
LESS
Read
0011
Q2
Q2
No
=
=
<
=
f
=
255
Address (HERE)
?
WREG;
Address (LESS)
WREG;
Address (NLESS)
CPFSLT REG
:
:
0000
operation
Process
Data
Q3
Q3
No
ffff
f
operation
operation
Q4
No
Q4
No
ffff
DAW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Example1:
Example 2:
Before Instruction
After Instruction
Before Instruction
After Instruction
Decode
WREG
REG1
C
DC
WREG
REG1
C
DC
WREG
REG1
C
DC
WREG
REG1
C
DC
Q1
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
register 'f'
Decimal Adjust WREG Register
[ label ] DAW
0
s
If [WREG<3:0> >9] .OR. [DC = 1] then
else
If [WREG<7:4> >9] .OR. [C = 1] then
else
C
DAW adjusts the eight bit value in
WREG resulting from the earlier addi-
tion of two variables (each in packed
BCD format) and produces a correct
packed BCD result.
s = 0:
s = 1:
1
1
DAW
Read
0010
Q2
WREG<3:0> + 6
WREG<3:0>
WREG<7:4> + 6
WREG<7:4>
0xA5
??
0
0
0x05
0x05
1
0
0xCE
??
0
0
0x24
0x24
1
0
f
[0,1]
1997 Microchip Technology Inc.
255
REG1, 0
Result is placed in Data
memory location 'f' and
Result is placed in Data
memory location 'f'.
WREG.
111s
Process
Data
Q3
f,s
f<3:0>, s<3:0>;
f<7:4>, s<7:4>
ffff
f<3:0>, s<3:0>;
f<7:4>, s<7:4>
register 'f'
and other
specified
register
Write
Q4
ffff