PIC17C756-16/L Microchip Technology, PIC17C756-16/L Datasheet - Page 97

• Manufacturer Part Number: PIC17C756-16/L
• Description: MICRO CTRL 16K MEMORY OTP 68PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 17Cr

Specifications of PIC17C756-16/L

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: OTP
• Ram Size: 902 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 68-PLCC
• For Use With: AC164308 - MODULE SKT FOR PM3 68PLCCDVA17XL681 - DEVICE ADAPTER FOR PIC17C752DM173001 - KIT DEVELOPMENT PICDEM17AC174007 - MODULE SKT PROMATEII 68PLCCAC164024 - ADAPTER PICSTART PLUS 68PLCC
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -

13.1.3
Three high speed pulse width modulation (PWM) out-
puts are provided. The PWM1 output uses Timer1 as
its time-base, while PWM2 and PWM3 may indepen-
dently be software configured to use either Timer1 or
Timer2 as the time-base. The PWM outputs are on the
RB2/PWM1, RB3/PWM2, and RG5/PWM3 pins.
Each PWM output has a maximum resolution of
10-bits. At 10-bit resolution, the PWM output frequency
is 32.2 kHz (@ 32 MHz clock) and at 8-bit resolution the
PWM output frequency is 128.9 kHz. The duty cycle of
the output can vary from 0% to 100%.
Figure 13-6 shows a simplified block diagram of a
PWM module.
The duty cycle registers are double buffered for glitch
free operation. Figure 13-7 shows how a glitch could
occur if the duty cycle registers were not double buff-
ered.
FIGURE 13-7: PWM OUTPUT
1997 Microchip Technology Inc.
PWM
output
Note
USING PULSE WIDTH MODULATION
(PWM) OUTPUTS WITH TIMER1 AND
TIMER2
In this example, PWM period = 50. Old duty cycle is 30. New duty cycle value is 10.
The dotted line shows PWM output if duty cycle registers were not double buffered.
If the new duty cycle is written after the timer has passed that value, then the PWM does
not reset at all during the current cycle causing a “glitch”.
Timer
interrupt
0
10
Write new
PWM value
20
30
Preliminary
40
0
Timer interrupt
new PWM value
transferred to slave
The user needs to set the PWM1ON bit (TCON2<4>)
to enable the PWM1 output. When the PWM1ON bit is
set, the RB2/PWM1 pin is configured as PWM1 output
and forced as an output irrespective of the data direc-
tion bit (DDRB<2>). When the PWM1ON bit is clear,
the pin behaves as a port pin and its direction is con-
trolled by its data direction bit (DDRB<2>). Similarly,
the PWM2ON (TCON2<5>) bit controls the configura-
tion of the RB3/PWM2 pin and the PWM3ON
(TCON3<0>) bit controls the configuration of the
RG5/PWM3 pin.
FIGURE 13-6: SIMPLIFIED PWM BLOCK
Note 1: 8-bit timer is concatenated with 2-bit internal Q clock
PWxDCH
(Slave)
Duty Cycle registers
Comparator
PRy
or 2 bits of the prescaler to create 10-bit time-base.
TMRx
Comparator
(Note 1)
DIAGRAM
Clear Timer,
PWMx pin and
Latch D.C.
Write
Read
PWxDCL<7:6>
R
S
Q
DS30264A-page 97
PWMxON
PWMx