PIC17C756-16/L Microchip Technology, PIC17C756-16/L Datasheet - Page 180

• Manufacturer Part Number: PIC17C756-16/L
• Description: MICRO CTRL 16K MEMORY OTP 68PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 17Cr

Specifications of PIC17C756-16/L

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: OTP
• Ram Size: 902 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 68-PLCC
• For Use With: AC164308 - MODULE SKT FOR PM3 68PLCCDVA17XL681 - DEVICE ADAPTER FOR PIC17C752DM173001 - KIT DEVELOPMENT PICDEM17AC174007 - MODULE SKT PROMATEII 68PLCCAC164024 - ADAPTER PICSTART PLUS 68PLCC
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -

17.4
The Power-down mode is entered by executing a
SLEEP instruction. This clears the Watchdog Timer and
postscaler (if enabled). The PD bit is cleared and the
TO bit is set (in the CPUSTA register). In SLEEP mode,
the oscillator driver is turned off. The I/O ports maintain
their status (driving high, low, or hi-impedance).
The MCLR/V
(V
MCLR/V
17.4.1
The device can wake-up from SLEEP through one of
the following events:
• POR
• External reset input on MCLR/V
• WDT Reset (if WDT was enabled)
• BOR
• Interrupt from RA0/INT pin, RB port change,
The following peripheral interrupts can wake the device
from SLEEP:
• Capture interrupts
• USART synchronous slave transmit interrupts
• USART synchronous slave receive interrupts
• A/D conversion complete
• SPI slave transmit / receive complete
• I
Other peripherals cannot generate interrupts since dur-
ing SLEEP, no on-chip Q clocks are present.
Any reset event will cause a device reset. Any interrupt
event is considered a continuation of program execu-
tion. The TO and PD bits in the CPUSTA register can
FIGURE 17-3: WAKE-UP FROM SLEEP THROUGH INTERRUPT
DS30264A-page 180
Note 1: XT or LF oscillator mode assumed.
(RA0/INT pin)
IHMC
T0CKI interrupt, or some peripheral Interrupts
INSTRUCTION FLOW
2
CLKOUT(4)
GLINTD bit
C slave receive
Instruction
executed
Instruction
fetched
2: Tost = 1024Tosc (drawing not to scale). This delay will not be there for RC osc mode.
3: When GLINTD = 0 processor jumps to interrupt routine after wake-up. If GLINTD = 1, execution will continue in line.
4: CLKOUT is not available in these osc modes, but shown here for timing reference.
INTF flag
PC
). A WDT time-out RESET does not drive the
OSC1
PP
Power-down Mode (SLEEP)
WAKE-UP FROM SLEEP
INT
pin low.
PP
pin must be at a logic high level
Inst (PC) = SLEEP
Q1
Inst (PC-1)
Q2
PC
Q3
Q4
PP
pin
Q1
Inst (PC+1)
SLEEP
Q2
PC+1
Q3
Preliminary
Q4
Processor
in SLEEP
Q1
Q2
be used to determine the cause of device reset. The
PD bit, which is set on power-up, is cleared when
SLEEP is invoked. The TO bit is cleared if WDT
time-out occurred (and caused wake-up).
When the SLEEP instruction is being executed, the next
instruction (PC + 1) is pre-fetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up is
regardless of the state of the GLINTD bit. If the GLINTD
bit is set (disabled), the device continues execution at
the instruction after the SLEEP instruction. If the
GLINTD bit is clear (enabled), the device executes the
instruction after the SLEEP instruction and then
branches to the interrupt vector address. In cases
where the execution of the instruction following SLEEP
is not desirable, the user should have a NOP after the
SLEEP instruction.
The WDT is cleared when the device wakes from
SLEEP, regardless of the source of wake-up.
17.4.1.1
When the oscillator type is configured in XT or LF
mode, the Oscillator Start-up Timer (OST) is activated
on wake-up. The OST will keep the device in reset for
1024T
considering the interrupt response time when coming
out of SLEEP.
PC+2
Note:
Q3
Tost(2)
OSC
Q4
. This needs to be taken into account when
If the global interrupt is disabled (GLINTD
is set), but any interrupt source has both its
interrupt enable bit and the corresponding
interrupt flag bit set, the device will imme-
diately wake-up from sleep. The TO bit is
set, and the PD bit is cleared.
WAKE-UP DELAY
Q1
Inst (PC+2)
Inst (PC+1)
Q2
0004h
Q3
1997 Microchip Technology Inc.
Q4
Interrupt Latency (2)
Q1
Dummy Cycle
Q2
0005h
Q3
Q4