PIC17C756-16/L Microchip Technology, PIC17C756-16/L Datasheet - Page 94

• Manufacturer Part Number: PIC17C756-16/L
• Description: MICRO CTRL 16K MEMORY OTP 68PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 17Cr

Specifications of PIC17C756-16/L

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: OTP
• Ram Size: 902 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 68-PLCC
• For Use With: AC164308 - MODULE SKT FOR PM3 68PLCCDVA17XL681 - DEVICE ADAPTER FOR PIC17C752DM173001 - KIT DEVELOPMENT PICDEM17AC174007 - MODULE SKT PROMATEII 68PLCCAC164024 - ADAPTER PICSTART PLUS 68PLCC
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -

13.1
13.1.1
Both Timer1 and Timer2 will operate in 8-bit mode
when the T16 bit is clear. These two timers can be inde-
pendently configured to increment from the internal
instruction cycle clock (T
source on the RB4/TCLK12 pin. The timer clock source
is configured by the TMRxCS bit (x = 1 for Timer1 or =
2 for Timer2). When TMRxCS is clear, the clock source
is internal and increments once every instruction cycle
(Fosc/4). When TMRxCS is set, the clock source is the
RB4/TCLK12 pin, and the counters will increment on
every falling edge of the RB4/TCLK12 pin.
The timer increments from 00h until it equals the Period
register (PRx). It then resets to 00h at the next incre-
ment cycle. The timer interrupt flag is set when the
timer is reset. TMR1 and TMR2 have individual inter-
rupt flag bits. The TMR1 interrupt flag bit is latched into
TMR1IF, and the TMR2 interrupt flag bit is latched into
TMR2IF.
Each timer also has a corresponding interrupt enable
bit (TMRxIE). The timer interrupt can be enabled/dis-
abled by setting/clearing this bit. For peripheral inter-
rupts to be enabled, the Peripheral Interrupt Enable bit
must be set (PEIE = '1') and global interrupt must be
enabled (GLINTD = '0').
The timers can be turned on and off under software
control. When the timer on control bit (TMRxON) is set,
the timer increments from the clock source. When
TMRxON is cleared, the timer is turned off and cannot
cause the timer interrupt flag to be set.
FIGURE 13-4: TIMER1 AND TIMER2 IN TWO 8-BIT TIMER/COUNTER MODE
DS30264A-page 94
Timer1 and Timer2
TIMER1, TIMER2 IN 8-BIT MODE
RB4/TCLK12
Fosc/4
Fosc/4
CY
) or from an external clock
TMR1CS
(TCON1<0>)
TMR2CS
(TCON1<1>)
1
0
0
1
TMR1ON
(TCON2<0>)
TMR2ON
(TCON2<1>)
Preliminary
Comparator<8>
Comparator<8>
Comparator x8
Comparator x8
13.1.1.1
When TMRxCS is set, the clock source is the
RB4/TCLK12 pin, and the counter will increment on
every falling edge on the RB4/TCLK12 pin. The
TCLK12 input is synchronized with internal phase
clocks. This causes a delay from the time a falling edge
appears on TCLK12 to the time TMR1 or TMR2 is actu-
ally incremented. For the external clock input timing
requirements, see the Electrical Specification section.
TMR1
TMR2
PR1
PR2
EXTERNAL CLOCK INPUT FOR TIMER1
AND TIMER2
Reset
Equal
Reset
Equal
1997 Microchip Technology Inc.
Set TMR1IF
(PIR1<4>)
Set TMR2IF
(PIR1<5>)