ATMEGA103-6AI Atmel, ATMEGA103-6AI Datasheet - Page 20

IC MCU 128K 6MHZ A/D IT 64TQFP

ATMEGA103-6AI

Manufacturer Part Number
ATMEGA103-6AI
Description
IC MCU 128K 6MHZ A/D IT 64TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA103-6AI

Core Processor
AVR
Core Size
8-Bit
Speed
6MHz
Connectivity
SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
32
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
For Use With
ATSTK501 - ADAPTER KIT FOR 64PIN AVR MCU
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA103-6AI
Manufacturer:
ATMEL
Quantity:
586
Status Register – SREG
20
ATmega103(L)
Table 2. ATmega103(L) I/O Space (Continued)
Note:
All the different ATmega103(L) I/Os and peripherals are placed in the I/O space. The dif-
ferent I/O locations are directly accessed by the IN and OUT instructions transferring
data between the 32 general purpose working registers and the I/O space. I/O Registers
within the address range $00 - $1F are directly bit-accessible using the SBI and CBI
instructions. In these registers, the value of single bits can be checked by using the
SBIS and SBIC instructions. Refer to the “Instruction Set Summary” on page 135 for
more details. When using the I/O specific instructions IN and OUT, the I/O Register
address $00 - $3F are used. When addressing I/O Registers as SRAM, $20 must be
added to this address. All I/O Register addresses throughout this document are shown
with the SRAM address in parentheses.
For compatibility with future devices, reserved bits should be written to zero if accessed.
Reserved I/O memory addresses should never be written.
Some of the Status Flags are cleared by writing a logical “1” to them. Note that the CBI
and SBI instructions will operate on all bits in the I/O Register, writing a one back into
any flag read as set, thus clearing the flag. The CBI and SBI instructions work with reg-
isters $00 to $1F only.
The different I/O and peripherals control registers are explained in the following
sections.
The AVR Status Register (SREG) at I/O space location $3F ($5F) is defined as:
• Bit 7 – I: Global Interrupt Enable
The Global Interrupt Enable bit must be set (one) for the interrupts to be enabled. The
individual interrupt enable control is then performed in separate control registers. If the
Global Interrupt Enable Register is cleared (zero), none of the interrupts are enabled
independent of the individual interrupt enable settings. The I-bit is cleared by hardware
after an interrupt has occurred and is set by the RETI instruction to enable subsequent
interrupts.
• Bit 6 – T: Bit Copy Storage
The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source
and destination for the operated bit. A bit from a register in the Register File can be cop-
Bit
$3F ($5F)
Read/Write
Initial Value
I/O Address (SRAM
Address)
$06 ($26)
$05 ($25)
$04 ($24)
$03 ($23)
$02 ($22)
$01 ($21)
$00 ($20)
Reserved and unused locations are not shown in the table.
R/W
7
0
I
R/W
6
T
0
Name
ADCSR
ADCH
ADCL
PORTE
DDRE
PINE
PINF
R/W
H
5
0
Function
ADC Control and Status Register
ADC Data Register High
ADC Data Register Low
Data Register, Port E
Data Direction Register, Port E
Input Pins, Port E
Input Pins, Port F
R/W
S
4
0
R/W
V
3
0
R/W
2
N
0
R/W
1
Z
0
R/W
C
0
0
0945I–AVR–02/07
SREG

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