ATMEGA103-6AI Atmel, ATMEGA103-6AI Datasheet - Page 50

IC MCU 128K 6MHZ A/D IT 64TQFP

ATMEGA103-6AI

Manufacturer Part Number
ATMEGA103-6AI
Description
IC MCU 128K 6MHZ A/D IT 64TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA103-6AI

Core Processor
AVR
Core Size
8-Bit
Speed
6MHz
Connectivity
SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
32
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
For Use With
ATSTK501 - ADAPTER KIT FOR 64PIN AVR MCU
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Bonase Electronics (HK) Co., Limited Bonase Electronics (HK) Co., Limited
Part Number:
ATMEGA103-6AI
Manufacturer:
ATMEL
Quantity:
586
Price:
Timer/Counter1 Control
Register B – TCCR1B
50
ATmega103(L)
Table 16. PWM Mode Select
• Bit 7 – ICNC1: Input Capture1 Noise Canceler (4 CKs)
When the ICNC1 bit is cleared (zero), the Input Capture Trigger Noise Canceler function
is disabled. The Input Capture is triggered at the first rising/falling edge sampled on the
Input Capture pin PD4(IC1) as specified. When the ICNC1 bit is set (one), four succes-
sive samples are measured on PD4(IC1), and all samples must be high/low according to
the Input Capture trigger specification in the ICES1 bit. The actual sampling frequency is
XTAL clock frequency.
• Bit 6 – ICES1: Input Capture1 Edge Select
While the ICES1 bit is cleared (zero), the Timer/Counter1 contents are transferred to the
Input Capture Register (ICR1) on the falling edge of the Input Capture pin – PD4(IC1).
While the ICES1 bit is set (one), the Timer/Counter1 contents are transferred to the
Input Capture Register on the rising edge of the Input Capture pin – PD4(IC1).
• Bits 5, 4 – Res: Reserved Bits
These bits are reserved bits in the ATmega103(L) and always read as zero.
• Bit 3 – CTC1: Clear Timer/Counter1 on Compare Match
When the CTC1 control bit is set (one), the Timer/Counter1 is reset to $0000 in the clock
cycle after a Compare A Match. If the CTC1 control bit is cleared, Timer/Counter1 con-
tinues counting and is unaffected by a compare match. Since the compare match is
detected in the CPU clock cycle following the match, this function will behave differently
when a prescaling higher than 1 is used for the Timer. When a prescaling of 1 is used
and the Compare A Register is set to C, the Timer will count as follows if CTC1 is set:
... | C-2 | C-1 | C | 0 | 1 | ...
When the prescaler is set to divide by 8, the Timer will count like this:
... | C-2, C-2, C-2, C-2, C-2, C-2, C-2, C-2 | C-1, C-1, C-1, C-1, C-1, C-1, C-1, C-1 | C, 0,
0, 0, 0, 0, 0, 0 | ...
In PWM mode, this bit has no effect.
Bit
$2E ($4E)
Read/Write
Initial Value
PWM11
0
1
1
ICNC1
R/W
7
0
PWM10
1
0
1
ICES1
R/W
6
0
Description
Timer/Counter1 is an 8-bit PWM.
Timer/Counter1 is a 9-bit PWM.
Timer/Counter1 is a 10-bit PWM.
R
5
0
R
4
0
CTC1
R/W
3
0
CS12
R/W
2
0
CS11
R/W
1
0
CS10
R/W
0
0
0945I–AVR–02/07
TCCR1B

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