ATMEGA103-6AI Atmel, ATMEGA103-6AI Datasheet - Page 9
Manufacturer Part Number
IC MCU 128K 6MHZ A/D IT 64TQFP
Specifications of ATMEGA103-6AI
POR, PWM, WDT
Number Of I /o
Program Memory Size
128KB (64K x 16)
Program Memory Type
4K x 8
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
-40°C ~ 85°C
Package / Case
For Use With
ATSTK501 - ADAPTER KIT FOR 64PIN AVR MCU
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
arate Interrupt Vector in the Interrupt Vector table at the beginning of the
Program memory. The different interrupts have priority in accordance with their Interrupt
Vector position. The lower the Interrupt Vector address, the higher the priority.
The memory spaces in the AVR architecture are all linear and regular memory maps.
Figure 5 shows the structure of the 32 general purpose working registers in the CPU.
Figure 5. AVR CPU General Purpose Working Registers
All the register operating instructions in the instruction set have direct and single-cycle
access to all registers. The only exception are the five constant arithmetic and logic
instructions SBCI, SUBI, CPI, ANDI and ORI between a constant and a register and the
LDI instruction for load immediate constant data. These instructions apply to the second
half of the registers in the Register File – R16..R31. The general SBC, SUB, CP, AND
and OR and all other operations between two registers or on a single register apply to
the entire Register File.
As shown in Figure 5, each register is also assigned a Data memory address, mapping
them directly into the first 32 locations of the user Data Space. Although not being phys-
ically implemented as SRAM locations, this memory organization provides great
flexibility in access of the registers, as the X-, Y-, and Z-registers can be set to index any
register in the file.
The 4K bytes of SRAM available for general data are implemented as addresses $0060
. . .
. . .
X-register High Byte
Y-register High Byte
Z-register High Byte
X-register Low Byte
Y-register Low Byte
Z-register Low Byte