ATMEGA103-6AI Atmel, ATMEGA103-6AI Datasheet - Page 54

IC MCU 128K 6MHZ A/D IT 64TQFP

ATMEGA103-6AI

Manufacturer Part Number
ATMEGA103-6AI
Description
IC MCU 128K 6MHZ A/D IT 64TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA103-6AI

Core Processor
AVR
Core Size
8-Bit
Speed
6MHz
Connectivity
SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
32
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
For Use With
ATSTK501 - ADAPTER KIT FOR 64PIN AVR MCU
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
54
ATmega103(L)
the value TOP. This prevents the occurrence of odd-length PWM pulses (glitches) in the
event of an unsynchronized OCR1A/OCR1B write. See Figure 35 for an example.
Figure 35. Effects on Unsynchronized OCR1 Latching
During the time between the write and the latch operation, a read from OCR1A or
OCR1B will read the contents of the temporary location. This means that the most
recently written value always will read out of OCR1A/B.
When the OCR1A/OCR1B contains $0000 or TOP, the output OC1A/OC1B is updated
t o l o w o r h i g h o n t h e n e x t c o m p a r e m a t c h a c c o r d i n g t o t h e s e t t i n g s o f
COM1A1/COM1A0 or COM1B1/COM1B0. This is shown in Table 20.
Note:
Table 20. PWM Outputs OCR1X = $0000 or TOP
Note:
In PWM mode, the Timer Overflow Flag1, TOV1, is set when the counter advances from
$0000. Timer Overflow Interrupt1 operates exactly as in normal Timer/Counter mode,
i.e., it is executed when TOV1 is set provided that Timer Overflow Interrupt1 and Global
Interrupts are enabled. This does also apply to the Timer Output Compare1 flags and
interrupts.
Note: X = A or B
COM1X1
Compare Value changes
If the Compare Register contains the TOP value and the prescaler is not in use
(CS12..CS10 = 001), the PWM output will not produce any pulse at all, because the up-
counting and down-counting value is reached simultaneously. When the prescaler is in
use (CS12..CS10 ≠ 001 or 000), the PWM output goes active when the counter reaches
the TOP value, but the down-counting compare match is not interpreted to be reached
before the next time the counter reaches the TOP value, making a one-period PWM
pulse.
X = A or B
1
1
1
1
Unsynchronized
Synchronized
Compare Value changes
COM1X0
0
0
1
1
OCR1X Latch
OCR1X Latch
OCR1X
$0000
$0000
TOP
TOP
Glitch
Compare Value
Counter Value
PWM Output OC1X
Output OC1X
Counter Value
Compare Value
PWM Output OC1X
H
H
L
L
0945I–AVR–02/07

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