ATMEGA169-16AI Atmel, ATMEGA169-16AI Datasheet
ATMEGA169-16AI
Specifications of ATMEGA169-16AI
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ATMEGA169-16AI Summary of contents
Page 1
... I/O and Packages – 53 Programmable I/O Lines – 64-lead TQFP and 64-pad QFN/MLF • Speed Grade: – ATmega169V MHz @ 1.8 - 5.5V MHz @ 2.7 - 5.5V – ATmega169 MHz @ 2.7 - 5.5V MHz @ 4.5 - 5.5V • Temperature range: – -40°C to 85°C Industrial • ...
Page 2
... Pin Configurations Disclaimer ATmega169/V 2 Figure 1. Pinout ATmega169 LCDCAP 1 (RXD/PCINT0) PE0 2 INDEX CORNER (TXD/PCINT1) PE1 3 (XCK/AIN0/PCINT2) PE2 4 (AIN1/PCINT3) PE3 5 (USCK/SCL/PCINT4) PE4 6 (DI/SDA/PCINT5) PE5 7 (DO/PCINT6) PE6 8 (CLKO/PCINT7) PE7 9 (SS/PCINT8) PB0 10 (SCK/PCINT9) PB1 11 (MOSI/PCINT10) PB2 12 (MISO/PCINT11) PB3 13 (OC0A/PCINT12) PB4 14 (OC1A/PCINT13) PB5 15 (OC1B/PCINT14) PB6 16 Note: The large center pad underneath the QFN/MLF packages is made of metal and internally connected to GND ...
Page 3
... Overview The ATmega169 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega169 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. Block Diagram Figure 2 ...
Page 4
... In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega169 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATmega169 AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Cir- cuit Emulators, and Evaluation kits. ...
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... The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port C also serves the functions of special features of the ATmega169 as listed on page 66. Port 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit) ...
Page 6
... The Port G pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port G also serves the functions of various special features of the ATmega169 as listed on page 70. Reset input. A low level on this pin for longer than the minimum pulse length will gener- ate a reset, even if the clock is not running ...
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... The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation typical ALU operation, two operands are output from the Register File, ATmega169/V Data Bus 8-bit Status ...
Page 8
... Registers, SPI, and other I/O functions. The I/O Memory can be accessed directly the Data Space locations following those of the Register File, 0x20 - 0x5F. In addition, the ATmega169 has Extended I/O space from 0x60 - 0xFF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used. ...
Page 9
... The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. • Bit 1 – Z: Zero Flag The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. ATmega169 ...
Page 10
... General Purpose Register File ATmega169/V 10 • Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruc- tion Set Description” for detailed information. The Register File is optimized for the AVR Enhanced RISC instruction set. In order to ...
Page 11
... AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present. Bit – – – SP7 SP6 SP5 Read/Write R/W R/W R/W R/W R/W R/W Initial Value ATmega169 R26 (0x1A R28 (0x1C R30 (0x1E – – SP10 SP9 SP4 SP3 SP2 SP1 4 ...
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... Instruction Execution Timing Reset and Interrupt Handling ATmega169/V 12 This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clk source for the chip. No internal clock division is used. Figure 6 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access Register File concept ...
Page 13
... EECR, EEWE out SREG, r16 ; restore SREG value (I-bit) C Code Example char cSREG; cSREG = SREG; /* store SREG value */ /* disable interrupts during timed sequence */ __disable_interrupt(); EECR |= (1<<EEMWE); /* start EEPROM write */ EECR |= (1<<EEWE); SREG = cSREG; /* restore SREG value (I-bit) */ ATmega169/V 13 ...
Page 14
... Interrupt Response Time ATmega169/V 14 When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in this example. Assembly Code Example sei ; set Global Interrupt Enable sleep ; enter sleep, waiting for interrupt ; note: will enter sleep before any pending ...
Page 15
... Boot Program section and Application Program section. The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATmega169 Program Counter (PC bits wide, thus addressing the 8K program memory locations. The operation of Boot Program section and associated Boot Lock bits for software protection are described in detail in “ ...
Page 16
... X, Y, and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O Registers, 160 Extended I/O Regis- ters, and the 1,024 bytes of internal data SRAM in the ATmega169 are all accessible through all these addressing modes. The Register File is described in “General Purpose Register File” ...
Page 17
... Data RD Memory Access Instruction The ATmega169 contains 512 bytes of data EEPROM memory organized as a sep- arate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register ...
Page 18
... Bits 7..4 – Res: Reserved Bits These bits are reserved bits in the ATmega169 and will always read as zero. • Bit 3 – EERIE: EEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant interrupt when EEWE is cleared. • ...
Page 19
... EEPROM, nor to change the EEAR Register. The calibrated Oscillator is used to time the EEPROM accesses. Table 1 lists the typical programming time for EEPROM access from the CPU. Table 1. EEPROM Programming Time Symbol Number of Calibrated RC Oscillator Cycles EEPROM write (from CPU) ATmega169/V Typ Programming Time 67 584 8 ...
Page 20
... ATmega169/V 20 The following code examples show one assembly and one C function for writing to the EEPROM. The examples assume that interrupts are controlled (e.g. by disabling inter- rupts globally) so that no interrupts will occur during execution of these functions. The examples also assume that no Flash Boot Loader is present in the software. If such code is present, the EEPROM write function must also wait for any ongoing SPM com- mand to finish ...
Page 21
... EEPROM, and the same design solutions should be applied. An EEPROM data corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the EEPROM requires a minimum voltage to operate correctly. Secondly, the CPU itself can execute instructions incorrectly, if the supply voltage is too low recommendation: ATmega169/V 21 ...
Page 22
... I/O Memory General Purpose I/O Registers The ATmega169 contains three General Purpose I/O Registers. These registers can be General Purpose I/O Register 2 – GPIOR2 General Purpose I/O Register 1 – GPIOR1 General Purpose I/O Register 0 – GPIOR0 ATmega169/V 22 Keep the AVR RESET active (low) during periods of insufficient power supply voltage. ...
Page 23
... The dedicated clock domain allows using this Timer/Counter as a real-time counter even when the device is in sleep mode. It also allows the LCD controller output to con- tinue while the rest of the device is in sleep mode. ATmega169/V CPU Core clk AVR Clock ...
Page 24
... The Watchdog Oscillator is used for timing this real-time part of the start-up time. The number of WDT Oscillator cycles used for each time-out is shown in Table 3. The frequency of the Watchdog Oscillator is voltage dependent as shown in “ATmega169 Typical Characteristics” on page 305. Table 3. Number of Watchdog Oscillator Cycles Typ Time-out ( ...
Page 25
... Notes: 1. This option should not be used with crystals, only with ceramic resonators. The CKSEL0 Fuse together with the SUT1..0 Fuses select the start-up times as shown in Table 5. ATmega169/V XTAL2 XTAL1 GND Recommended Range for Capacitors C1 and C2 for Use with Crystals (pF) – ...
Page 26
... Low-frequency Crystal Oscillator ATmega169/V 26 Table 5. Start-up Times for the Crystal Oscillator Clock Selection Start-up Time from Power-down and CKSEL0 SUT1..0 Power-save 0 00 258 258 16K 16K 16K CK 1 Notes: 1. These options should only be used when not operating close to the maximum fre- quency of the device, and only if frequency stability at start-up is not important for the application ...
Page 27
... Table 9. Start-up times for the internal calibrated RC Oscillator clock selection Start-up Time from Power- SUT1..0 down and Power-save ( Note: 1. The device is shipped with this option selected. ATmega169/V Recommended Usage 1K CK Stable frequency at start-up (1) Nominal Frequency 8.0 MHz Additional Delay from Reset (V = 5.0V) Recommended Usage CC 14CK BOD enabled 14CK + 4 ...
Page 28
... Oscillator Calibration Register – OSCCAL External Clock ATmega169/V 28 Bit – CAL6 CAL5 Read/Write R R/W R/W Initial Value Device Specific Calibration Value • Bits 6..0 – CAL6..0: Oscillator Calibration Value Writing the calibration byte to this address will trim the internal Oscillator to remove pro- cess variations from the Oscillator frequency ...
Page 29
... The ATmega169 system clock can be divided by setting the “Clock Prescale Register – CLKPR” on page 30. This feature can be used to decrease the system clock frequency and power consumption when the requirement for processing power is low. This can be used with all clock source options, and it will affect the clock frequency of the CPU and all synchronous peripherals ...
Page 30
... Clock Prescale Register – CLKPR ATmega169/V 30 time the CLKPS values are written, it takes between and T1 + 2*T2 before the new clock frequency is active. In this interval, 2 active clock edges are produced. Here the previous clock period, and T2 is the period corresponding to the new prescaler setting ...
Page 31
... Table 13. Clock Prescaler Select CLKPS3 CLKPS2 CLKPS1 ATmega169/V CLKPS0 Clock Division Factor Reserved 1 0 Reserved 1 1 Reserved 0 0 Reserved 0 1 Reserved 1 0 Reserved 1 1 Reserved 128 256 31 ...
Page 32
... If a reset occurs during sleep mode, the MCU wakes up and executes from the Reset Vector. Figure 11 on page 23 presents the different clock systems in the ATmega169, and their distribution. The figure is helpful in selecting an appropriate sleep mode. The Sleep Mode Control Register contains control bits for power management. ...
Page 33
... Timer/Counter2 if the corresponding Timer/Counter2 interrupt enable bits are set in TIMSK2, and the Global Interrupt Enable bit in SREG is set. It can also wake up from an LCD controller interrupt. If neither Timer/Counter2 nor the LCD controller is running, Power-down mode is rec- ommended instead of Power-save mode. ATmega169/V and clk , while allowing the CPU FLASH ...
Page 34
... In all other sleep modes, the clock is already stopped. Bit – – – Read/Write Initial Value • Bit 7..5 - Res: Reserved bits These bits are reserved in ATmega169 and will always read as zero. Wake-up Sources USI Start LCD EEPROM e Condition Controller Timer2 Ready (3) (2) (2) X ...
Page 35
... Analog Comparator is set up to use the Internal Voltage Reference as input, the Analog Comparator should be disabled in all sleep modes. Otherwise, the Internal Voltage Ref- erence will be enabled, independent of sleep mode. Refer to “Analog Comparator” on page 190 for details on how to configure the Analog Comparator. ATmega169/V 35 ...
Page 36
... Watchdog Timer Port Pins JTAG Interface and On-chip Debug System ATmega169 the Brown-out Detector is not needed by the application, this module should be turned off. If the Brown-out Detector is enabled by the BODLEVEL Fuses, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this will contribute significantly to the total current consumption. Refer to “ ...
Page 37
... The time-out period of the delay counter is defined by the user through the SUT and CKSEL Fuses. The different selections for the delay period are presented in “Clock Sources” on page 24. The ATmega169 has five sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V ) ...
Page 38
... ATmega169/V 38 Figure 14. Reset Logic Power-on Reset Circuit Brown-out BODLEVEL [2..0] Reset Circuit Pull-up Resistor SPIKE FILTER JTAG Reset Register Watchdog Oscillator Generator CKSEL[3:0] SUT[1:0] Table 16. Reset Characteristics Symbol Parameter Power-on Reset Threshold Voltage (rising) V POT Power-on Reset Threshold (1) Voltage (falling) V RESET Pin Threshold Voltage ...
Page 39
... V CC Figure 15. MCU Start-up, RESET Tied POT RST RESET t TOUT TIME-OUT INTERNAL RESET Figure 16. MCU Start-up, RESET Extended Externally V POT V CC RESET TIME-OUT INTERNAL RESET ATmega169/V rise. The RESET signal is activated CC decreases below the detection level RST t TOUT is below the CC 39 ...
Page 40
... MCU after the Time-out period – t Figure 17. External Reset During Operation CC ATmega169 has an On-chip Brown-out Detection (BOD) circuit for monitoring the V level during operation by comparing fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection ...
Page 41
... This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by the JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset writing a logic zero to the flag. ATmega169/V decreases to a value below the trigger level ( the voltage stays below the trigger level ...
Page 42
... Reset Flags. ATmega169 features an internal bandgap reference. This reference is used for Brown- out Detection, and it can be used as an input to the Analog Comparator or the ADC. The voltage reference has a start-up time that may influence the way it should be used. ...
Page 43
... Bits 7..5 – Res: Reserved Bits These bits are reserved bits in the ATmega169 and will always read as zero. • Bit 4 – WDCE: Watchdog Change Enable This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not be disabled ...
Page 44
... ATmega169/V 44 • Bit 3 – WDE: Watchdog Enable When the WDE is written to logic one, the Watchdog Timer is enabled, and if the WDE is written to logic zero, the Watchdog Timer function is disabled. WDE can only be cleared if the WDCE bit has logic level one. To disable an enabled Watchdog Timer, the follow- ing procedure must be followed: 1 ...
Page 45
... In the same operation, write a logical one to WDCE and WDE. Even though the WDE always is set, the WDE must be written to one to start the timed sequence. 2. Within the next four clock cycles, in the same operation, write the WDP bits as desired, but with the WDCE bit cleared. The value written to the WDE bit is irrelevant. ATmega169/V 45 ...
Page 46
... Interrupts Interrupt Vectors in ATmega169 ATmega169/V 46 This section describes the specifics of the interrupt handling as performed in ATmega169. For a general explanation of the AVR interrupt handling, refer to “Reset and Interrupt Handling” on page 12. Table 22. Reset and Interrupt Vectors Vector Program (2) No. Address Source (1) 1 0x0000 ...
Page 47
... The Boot Reset Address is shown in Table 113 on page 264. For the BOOTRST Fuse “1” means unprogrammed while “0” means programmed. The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega169 is: Address Labels Code 0x0000 ...
Page 48
... ATmega169/V 48 When the BOOTRST Fuse is unprogrammed, the Boot section size set to 2K bytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: ...
Page 49
... Interrupt Vectors are placed in the Application section and Boot Lock bit BLB12 is pro- gramed, interrupts are disabled while executing from the Boot Loader section. Refer to the section “Boot Loader Support – Read-While-Write Self-Programming” on page 252 for details on Boot Lock bits. ATmega169/V Comments ; Reset handler ; IRQ0 Handler ...
Page 50
... ATmega169/V 50 • Bit 0 – IVCE: Interrupt Vector Change Enable The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable interrupts, as explained in the IVSEL description above. See Code Example below ...
Page 51
... SUT and CKSEL Fuses as described in “System Clock and Clock Options” on page 23. An example of timing of a pin change interrupt is shown in Figure 21. Figure 21. Pin Change Interrupt pin_lat PCINT( pin_sync LE clk PCINT(0) in PCMSK(x) clk PCINT(n) pin_lat pin_sync pcint_in_(n) pcint_syn pcint_setflag PCIF ATmega169/V pcint_in_(0) 0 pcint_syn pcint_setflag x clk PCIF 51 ...
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... External Interrupt Control Register A – EICRA ATmega169/V 52 The External Interrupt Control Register A contains control bits for interrupt sense control. Bit – – – Read/Write Initial Value • Bit 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0 The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask are set ...
Page 53
... If the I-bit in SREG and the PCIE0 bit in EIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the inter- rupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. ATmega169 ...
Page 54
... Pin Change Mask Register 1 – PCMSK1 Pin Change Mask Register 0 – PCMSK0 ATmega169/V 54 • Bit 0 – INTF0: External Interrupt Flag 0 When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes set (one). If the I-bit in SREG and the INT0 bit in EIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector ...
Page 55
... Most port pins are multiplexed with alternate functions for the peripheral fea- tures on the device. How each alternate function interferes with the port pin is described in “Alternate Port Functions” on page 60. Refer to the individual module sections for a full description of the alternate functions. ATmega169 Logic See Figure " ...
Page 56
... Ports as General Digital I/O Configuring the Pin ATmega169/V 56 Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. The ports are bi-directional I/O ports with optional internal pull-ups. Figure 23 shows a functional description of one I/O-port pin, here generically called Pxn ...
Page 57
... The maximum and minimum propagation delays are denoted t respectively. Figure 24. Synchronization when Reading an Externally Applied Pin value SYSTEM CLK INSTRUCTIONS XXX SYNC LATCH PINxn r17 ATmega169/V I/O Pull-up Comment Input No Tri-state (Hi-Z) Pxn will source current if ext. pulled Input Yes low ...
Page 58
... ATmega169/V 58 Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock goes low ...
Page 59
... Rising Edge, Falling Edge, or Any Logic Change on Pin” while the external interrupt is not enabled, the corresponding External Interrupt Flag will be set when resuming from the above mentioned Sleep mode, as the clamping in these sleep mode produces the requested logic change. ATmega169/V 59 ...
Page 60
... Unconnected Pins Alternate Port Functions ATmega169 some pins are unused recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described above, floating inputs should be avoided to reduce current consumption in all other modes where the digital inputs are enabled (Reset, Active mode and Idle mode). ...
Page 61
... The following subsections shortly describe the alternate functions for each port, and relate the overriding signals to the alternate function. Refer to the alternate function description for further details. ATmega169/V Description If this signal is set, the pull-up enable is controlled by the PUOV signal. If this signal is cleared, the pull-up is enabled when {DDxn, PORTxn, PUD} = 0b010 ...
Page 62
... MCU Control Register – MCUCR Alternate Functions of Port A ATmega169/V 62 Bit JTD – – Read/Write R Initial Value • Bit 4 – PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). ...
Page 63
... The OC2A pin is also the output pin for the PWM mode timer function. PCINT15, Pin Change Interrupt source 15: The PB7 pin can serve as an external inter- rupt source. ATmega169/V PA2/COM2 PA1/COM1 LCDEN • LCDEN • ...
Page 64
... ATmega169/V 64 • OC1B/PCINT14, Bit 6 OC1B, Output Compare Match B output: The PB6 pin can serve as an external output for the Timer/Counter1 Output Compare B. The pin has to be configured as an output (DDB6 set (one)) to serve this function. The OC1B pin is also the output pin for the PWM mode timer function ...
Page 65
... OC1B ENABLE PVOV OC2A OC1B PTOE – – DIEOE PCINT15 • PCINT14 • PCIE1 PCIE1 DIEOV PCINT15 INPUT PCINT14 INPUT AIO – – ATmega169/V PB5/OC1A/ PB4/OC0A/ PCINT13 PCINT12 OC1A ENABLE OC0A ENABLE OC1A OC0A – – PCINT13 • PCIE1 PCINT12 • ...
Page 66
... Alternate Functions of Port C ATmega169/V 66 Table 32. Overriding Signals for Alternate Functions in PB3..PB0 Signal PB3/MISO/ PB2/MOSI/ Name PCINT11 PCINT10 PUOE SPE • MSTR SPE • MSTR PUOV PORTB3 • PUD PORTB2 • PUD DDOE SPE • MSTR SPE • MSTR DDOV 0 0 PVOE SPE • ...
Page 67
... DDOE LCDEN LCDEN DDOV 0 0 PVOE 0 0 PVOV 0 0 PTOE – – DIEOE LCDEN LCDEN DIEOV – – AIO SEG9 SEG10 ATmega169/V PC5/SEG7 PC4/SEG8 LCDEN LCDEN 0 0 LCDEN LCDEN – – LCDEN LCDEN 0 0 – – SEG7 SEG8 PC1/SEG11 PC0/SEG12 LCDEN ...
Page 68
... Alternate Functions of Port D ATmega169/V 68 The Port D pins with alternate functions are shown in Table 36. Table 36. Port D Pins Alternate Functions Port Pin Alternate Function PD7 SEG15 (LCD front plane 15) PD6 SEG16 (LCD front plane 16) PD5 SEG17 (LCD front plane 17) PD4 SEG18 (LCD front plane 18) ...
Page 69
... PVOE 0 0 PVOV 0 0 PTOE – – DIEOE LCDEN • LCDEN • (LCDPM>3) (LCDPM>3) DIEOV – – AIO – – ATmega169/V PD5/SEG17 PD4/SEG18 LCDEN • LCDEN • (LCDPM>2) (LCDPM> LCDEN • LCDEN • (LCDPM>2) (LCDPM> – – LCDEN • LCDEN • ...
Page 70
... Alternate Functions of Port E ATmega169/V 70 The Port E pins with alternate functions are shown in Table 39. Table 39. Port E Pins Alternate Functions Port Pin Alternate Function PCINT7 (Pin Change Interrupt7) PE7 CLKO (Divided System Clock) PE6 DO/PCINT6 (USI Data Output or Pin Change Interrupt6) PE5 DI/SDA/PCINT5 (USI Data Input or TWI Serial DAta or Pin Change Interrupt5) ...
Page 71
... PCINT7 • PCINT6 • PCIE0 PCIE0 DIEOV PCINT7 PCINT6 INPUT INPUT AIO – – Note: 1. CKOUT is one if the CKOUT Fuse is programmed ATmega169/V PE5/DI/SDA/ PE4/USCK/SCL/ PCINT5 PCINT4 USI_TWO-WIRE USI_TWO-WIRE USI_TWO-WIRE (SDA + PORTE5) • (USI_SCL_HOLD + DDE5 PORTE4) + DDE4 USI_TWO-WIRE • USI_TWO-WIRE • DDE5 ...
Page 72
... Alternate Functions of Port F ATmega169/V 72 Table 41. Overriding Signals for Alternate Functions in PE3..PE0 Signal PE3/AIN1/ PE2/XCK/AIN0/ Name PCINT3 PCINT2 PUOE 0 0 PUOV 0 0 DDOE 0 0 DDOV 0 0 PVOE 0 XCK OUTPUT ENABLE PVOV 0 XCK PTOE – – DIEOE (PCINT3 • (PCINT2 • PCIE0) + ...
Page 73
... JTAGEN JTAGEN DDOV 0 SHIFT_IR + SHIFT_DR PVOE 0 JTAGEN PVOV 0 TDO PTOE – – DIEOE JTAGEN JTAGEN DIEOV – – AIO TDI ADC6 INPUT ADC7 INPUT ATmega169 PF5/ADC5/TMS PF4/ADC4/TCK JTAGEN JTAGEN 1 1 JTAGEN JTAGEN – – JTAGEN JTAGEN 0 0 – – TMS TCK ...
Page 74
... Alternate Functions of Port G ATmega169/V 74 Table 44. Overriding Signals for Alternate Functions in PF3..PF0 Signal Name PF3/ADC3 PF2/ADC2 PUOE 0 0 PUOV 0 0 DDOE 0 0 DDOV 0 0 PVOE 0 0 PVOV 0 0 PTOE – – DIEOE 0 0 DIEOV – – AIO ADC3 INPUT ADC2 INPUT The alternate pin configuration is as follows: Table 45 ...
Page 75
... PVOV 0 0 PTOE – – DIEOE LCDEN • LCDEN (LCDPM>6) DIEOV INPUT – AIO SEG24 SEG4 ATmega169/V PG4/T0/SEG23 LCDEN • (LCDPM>5) 0 LCDEN • (LCDPM> – – LCDEN • (LCDPM> INPUT SEG23 PG1/SEG13 PG0/SEG14 LCDEN • LCDEN • (LCDPM>0) (LCDPM> LCDEN • ...
Page 76
... Port A Input Pins Address – PINA Port B Data Register – PORTB Port B Data Direction Register – DDRB Port B Input Pins Address – PINB Port C Data Register – PORTC Port C Data Direction Register – DDRC ATmega169/V 76 Bit PORTA7 PORTA6 PORTA5 Read/Write R/W ...
Page 77
... N/A N/A Bit PORTF7 PORTF6 PORTF5 Read/Write R/W R/W R/W Initial Value Bit DDF7 DDF6 DDF5 Read/Write R/W R/W R/W Initial Value ATmega169 PINC4 PINC3 PINC2 PINC1 R/W R/W R/W R/W N/A N/A N/A N PORTD4 PORTD3 PORTD2 PORTD1 R/W R/W R/W R ...
Page 78
... Port F Input Pins Address – PINF Port G Data Register – PORTG Port G Data Direction Register – DDRG Port G Input Pins Address – PING ATmega169/V 78 Bit PINF7 PINF6 PINF5 Read/Write R/W R/W R/W Initial Value N/A N/A N/A Bit – – – ...
Page 79
... Overflow and Compare Match Interrupt Sources (TOV0 and OCF0A) A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 27. For the actual placement of I/O pins, refer to “Pinout ATmega169” on page 2. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the “ ...
Page 80
... Definitions Timer/Counter Clock Sources Counter Unit ATmega169/V 80 event will also set the Compare Flag (OCF0A) which can be used to generate an Output Compare interrupt request. Many register and bit references in this section are written in general form. A lower case “n” replaces the Timer/Counter number, in this case 0. A lower case “x” replaces the Output Compare unit number, in this case unit A ...
Page 81
... Operation” on page 84.). Figure 29 shows a block diagram of the Output Compare unit. Figure 29. Output Compare Unit, Block Diagram OCRnx top bottom Waveform Generator FOCn ATmega169/V ). clk can be generated from an external or internal T0 is present or not. A CPU write overrides (has T0 DATA BUS TCNTn ...
Page 82
... Compare Match Blocking by TCNT0 Write Using the Output Compare Unit ATmega169/V 82 The OCR0A Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR0 Compare Register to either top or bottom of the counting sequence ...
Page 83
... PWM mode, refer to Table 51 on page 90, and for phase correct PWM refer to Table 52 on page 91. A change of the COM0A1:0 bits state will have effect at the first compare match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the FOC0A strobe bits. ATmega169 OCnx ...
Page 84
... Modes of Operation Normal Mode Clear Timer on Compare Match (CTC) Mode ATmega169/V 84 The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is defined by the combination of the Waveform Generation mode (WGM01:0) and Compare Output mode (COM0A1:0) bits. The Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do ...
Page 85
... The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent compare matches between OCR0A and TCNT0. Figure 32. Fast PWM Mode, Timing Diagram TCNTn OCnx OCnx Period ATmega169/V f clk_I/O = ------------------------------------------------- - ⋅ ⋅ ...
Page 86
... Phase Correct PWM Mode ATmega169/V 86 The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches MAX. If the interrupt is enabled, the interrupt handler routine can be used for updating the com- pare value. In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0A pin ...
Page 87
... OCR0A changes its value from MAX, like in Figure 33. When the OCR0A value is MAX the OCn pin value is the same as the result of a down-counting Compare Match. To ensure symmetry around BOTTOM the OCn value at MAX must correspond to the result of an up-counting Compare Match. ATmega169/V OCnx Interrupt Flag Set OCRnx Update TOVn Interrupt Flag Set ...
Page 88
... Timer/Counter Timing Diagrams ATmega169/V 88 • The timer starts counting from a value higher than the one in OCR0A, and for that reason misses the Compare Match and hence the OCn change that would have happened on the way up. The Timer/Counter is a synchronous design and the timer clock (clk shown as a clock enable signal in the following figures ...
Page 89
... Modes of oper- ation supported by the Timer/Counter unit are: Normal mode, Clear Timer on Compare match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes. See Table 49 and “Modes of Operation” on page 84. ATmega169/V TOP BOTTOM TOP ...
Page 90
... ATmega169/V 90 Table 49. Waveform Generation Mode Bit Description WGM01 WGM00 Timer/Counter Mode (CTC0) (PWM0) Mode of Operation Normal PWM, Phase Correct CTC Fast PWM Note: 1. The CTC0 and PWM0 bit definition names are now obsolete. Use the WGM01:0 def- initions. However, the functionality and location of these bits are compatible with previous versions of the timer. • ...
Page 91
... The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter. Writing to the TCNT0 Register blocks (removes) the compare match on the following timer clock. Modifying the counter (TCNT0) while the counter is running, introduces a risk of missing a compare match between TCNT0 and the OCR0A Register. ATmega169/V ( ...
Page 92
... Output Compare Register A – OCR0A Timer/Counter 0 Interrupt Mask Register – TIMSK0 Timer/Counter 0 Interrupt Flag Register – TIFR0 ATmega169/V 92 Bit Read/Write R/W R/W R/W Initial Value The Output Compare Register A contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an Output Compare interrupt generate a waveform output on the OC0A pin ...
Page 93
... Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling. The external clock must be guaranteed to have less than half the system clock frequency (f ATmega169/V ). Alternatively, one of four taps from the pres- CLK_I/O /1024. ...
Page 94
... General Timer/Counter Control Register – GTCCR ATmega169/V 94 the edge detector uses sampling, the maximum frequency of an external clock it can detect is half the sampling frequency (Nyquist sampling theorem). However, due to vari- ation of the system clock frequency and duty cycle caused by Oscillator source (crystal, ...
Page 95
... A simplified block diagram of the 16-bit Timer/Counter is shown in Figure 40. For the actual placement of I/O pins, refer to “Pinout ATmega169” on page 2. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the “16-bit Timer/Counter Register Description” ...
Page 96
... Registers ATmega169/V 96 Figure 40. 16-bit Timer/Counter Block Diagram Count Clear Direction Timer/Counter TCNTn = OCRnA = OCRnB ICRn TCCRnA Note: 1. Refer to Figure 1 on page 2, Table 29 on page 63, and Table 35 on page 67 for Timer/Counter1 pin placement and description. The Timer/Counter (TCNT1), Output Compare Registers (OCR1A/B), and Input Capture Register (ICR1) are all 16-bit registers. Special procedures must be followed when accessing the 16-bit registers. These procedures are described in the section “ ...
Page 97
... PWM11 is changed to WGM11. • CTC1 is changed to WGM12. The following bits are added to the 16-bit Timer/Counter Control Registers: • FOC1A and FOC1B are added to TCCR1C. • WGM13 is added to TCCR1B. The 16-bit Timer/Counter has improvements that will affect the compatibility in some special cases. ATmega169/V 97 ...
Page 98
... Accessing 16-bit Registers ATmega169/V 98 The TCNT1, OCR1A/B, and ICR1 are 16-bit registers that can be accessed by the AVR CPU via the 8-bit data bus. The 16-bit register must be byte accessed using two read or write operations. Each 16-bit timer has a single 8-bit register for temporary storing of the high byte of the 16-bit access ...
Page 99
... Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ __disable_interrupt(); /* Read TCNT1 into TCNT1; /* Restore global interrupt flag */ SREG = sreg; return i; } Note: 1. See “About Code Examples” on page 6. The assembly code example returns the TCNT1 value in the r17:r16 register pair. ATmega169/V 99 ...
Page 100
... Reusing the Temporary High Byte Register ATmega169/V 100 The following code examples show how atomic write of the TCNT1 Register contents. Writing any of the OCR1A/B or ICR1 Registers can be done by using the same principle. (1) Assembly Code Example TIM16_WriteTCNT1: ; Save global interrupt flag in r18,SREG ...
Page 101
... The counting sequence is determined by the setting of the Waveform Generation mode bits (WGM13:0) located in the Timer/Counter Control Registers A and B (TCCR1A and TCCR1B). There are close connections between how the counter behaves (counts) and ATmega169/V TOVn (Int.Req.) Clock Select ...
Page 102
... Input Capture Unit ATmega169/V 102 how waveforms are generated on the Output Compare outputs OC1x. For more details about advanced counting sequences and waveform generation, see “Modes of Opera- tion” on page 107. The Timer/Counter Overflow Flag (TOV1) is set according to the mode of operation selected by the WGM13:0 bits ...
Page 103
... ICR1 Register has been read. After a change of the edge, the Input Capture Flag (ICF1) must be cleared by software (writing a logical one to the I/O bit location). For measuring frequency only, the clearing of the ICF1 Flag is not required (if an interrupt handler is used). ATmega169/V 103 ...
Page 104
... Output Compare Units ATmega169/V 104 The 16-bit comparator continuously compares TCNT1 with the Output Compare Regis- ter (OCR1x). If TCNT equals OCR1x the comparator signals a match. A match will set the Output Compare Flag (OCF1x) at the next timer clock cycle. If enabled (OCIE1x = 1), the Output Compare Flag generates an Output Compare interrupt. The OCF1x Flag is automatically cleared when the interrupt is executed ...
Page 105
... Output Compare (FOC1x) strobe bits in Normal mode. The OC1x Register keeps its value even when changing between Waveform Generation modes. Be aware that the COM1x1:0 bits are not double buffered together with the compare value. Changing the COM1x1:0 bits will take effect immediately. ATmega169/V 105 ...
Page 106
... Compare Match Output Unit ATmega169/V 106 The Compare Output mode (COM1x1:0) bits have two functions. The Waveform Gener- ator uses the COM1x1:0 bits for defining the Output Compare (OC1x) state at the next compare match. Secondly the COM1x1:0 bits control the OC1x pin output source. Fig- ure 44 shows a simplified schematic of the logic affected by the COM1x1:0 bit setting ...
Page 107
... The Output Compare units can be used to generate interrupts at some given time. Using the Output Compare to generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time. ATmega169/V 107 ...
Page 108
... Clear Timer on Compare Match (CTC) Mode ATmega169/V 108 In Clear Timer on Compare or CTC mode (WGM13 12), the OCR1A or ICR1 Register are used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter value (TCNT1) matches either the OCR1A (WGM13 the ICR1 (WGM13:0 = 12). The OCR1A or ICR1 define the top value for the counter, hence also its resolution ...
Page 109
... OC1A or ICF1 Flag is set at the same timer clock cycle as TOV1 is set when either OCR1A or ICR1 is used for defining the TOP value. If one of the interrupts are enabled, the interrupt handler routine can be used for updating the TOP and com- pare values. ATmega169 log ...
Page 110
... ATmega169/V 110 When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the Compare Registers. If the TOP value is lower than any of the Compare Registers, a compare match will never occur between the TCNT1 and the OCR1x. Note that when using fixed TOP values the unused bits are masked to zero when any of the OCR1x Registers are written ...
Page 111
... PWM outputs. The small horizontal line marks on the TCNT1 slopes repre- sent compare matches between OCR1x and TCNT1. The OC1x Interrupt Flag will be set when a compare match occurs. Figure 47. Phase Correct PWM Mode, Timing Diagram TCNTn OCnx OCnx Period 1 ATmega169 log TOP + 1 = ---------------------------------- - ...
Page 112
... ATmega169/V 112 The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches BOT- TOM. When either OCR1A or ICR1 is used for defining the TOP value, the OC1A or ICF1 Flag is set accordingly at the same timer clock cycle as the OCR1x Registers are updated with the double buffer value (at TOP). The Interrupt Flags can be used to gen- erate an interrupt each time the counter reaches the TOP or BOTTOM value ...
Page 113
... PWM outputs. The small horizontal line marks on the TCNT1 slopes represent compare matches between OCR1x and TCNT1. The OC1x Interrupt Flag will be set when a com- pare match occurs. Figure 48. Phase and Frequency Correct PWM Mode, Timing Diagram TCNTn OCnx OCnx Period 1 2 ATmega169 log TOP + 1 = ---------------------------------- - ...
Page 114
... ATmega169/V 114 The Timer/Counter Overflow Flag (TOV1) is set at the same timer clock cycle as the OCR1x Registers are updated with the double buffer value (at BOTTOM). When either OCR1A or ICR1 is used for defining the TOP value, the OC1A or ICF1 Flag set when TCNT1 has reached TOP. The Interrupt Flags can then be used to generate an interrupt each time the counter reaches the TOP or BOTTOM value ...
Page 115
... PWM mode the OCR1x Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on. The same renaming applies for modes that set the TOV1 Flag at BOTTOM. ATmega169/V OCRnx OCRnx + 1 OCRnx Value ...
Page 116
... ATmega169/V 116 Figure 51. Timer/Counter Timing Diagram, no Prescaling clk I/O clk Tn (clk /1) I/O TCNTn TOP - 1 (CTC and FPWM) TCNTn TOP - 1 (PC and PFC PWM) TOVn (FPWM) and ICFn (if used as TOP) OCRnx Old OCRnx Value (Update at TOP) Figure 52 shows the same timing data, but with the prescaler enabled. ...
Page 117
... Note special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. In this case the compare match is ignored, but the set or clear is done at BOT- TOM. See “Fast PWM Mode” on page 109. for more details. ATmega169 COM1B0 – – WGM11 WGM10 R/W ...
Page 118
... ATmega169/V 118 Table 57 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the phase correct or the phase and frequency correct, PWM mode. Table 57. Compare Output Mode, Phase Correct and Phase and Frequency Correct (1) PWM COM1A1/COM1B1 COM1A0/COM1B0 Note special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. See “ ...
Page 119
... ICES1 bit is written to one, a rising (positive) edge will trigger the capture. When a capture is triggered according to the ICES1 setting, the counter value is copied into the Input Capture Register (ICR1). The event will also set the Input Capture Flag ATmega169/V Update of x TOP ...
Page 120
... Timer/Counter1 Control Register C – TCCR1C ATmega169/V 120 (ICF1), and this can be used to cause an Input Capture Interrupt, if this interrupt is enabled. When the ICR1 is used as TOP value (see description of the WGM13:0 bits located in the TCCR1A and the TCCR1B Register), the ICP1 is disconnected and consequently the Input Capture function is disabled. • ...
Page 121
... The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are written simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. See “Accessing 16-bit Registers” on page 98. ATmega169 ...
Page 122
... Input Capture Register 1 – ICR1H and ICR1L Timer/Counter1 Interrupt Mask Register – TIMSK1 ATmega169/V 122 Bit Read/Write R/W R/W R/W Initial Value The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the ICP1 pin (or optionally on the Analog Comparator output for Timer/Counter1). ...
Page 123
... TOV1 Flag is set when the timer overflows. Refer to Table 58 on page 119 for the TOV1 Flag behavior when using another WGM13:0 bit setting. TOV1 is automatically cleared when the Timer/Counter1 Overflow Interrupt Vector is executed. Alternatively, TOV1 can be cleared by writing a logic one to its bit location. ATmega169 ...
Page 124
... Allows Clocking from External 32 kHz Watch Crystal Independent of the I/O Clock A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 53. For the actual placement of I/O pins, refer to “Pinout ATmega169” on page 2. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the “ ...
Page 125
... Signal description (internal signals): count Increment or decrement TCNT2 by 1. direction Selects between increment and decrement. clear Clear TCNT2 (set all bits to zero). clk Timer/Counter clock. T2 ATmega169 default equal to the MCU clock, clk T2 TOVn (Int.Req.) clk Tn Control Logic Prescaler top ). T2 ...
Page 126
... Output Compare Unit ATmega169/V 126 top Signalizes that TCNT2 has reached maximum value. bottom Signalizes that TCNT2 has reached minimum value (zero). Depending on the mode of operation used, the counter is cleared, incremented, or dec- remented at each timer clock (clk T2 clock source, selected by the Clock Select bits (CS22:0). When no clock source is selected (CS22 the timer is stopped ...
Page 127
... Output Compare (FOC2A) strobe bit in Normal mode. The OC2A Register keeps its value even when changing between Waveform Generation modes. Be aware that the COM2A1:0 bits are not double buffered together with the compare value. Changing the COM2A1:0 bits will take effect immediately. ATmega169/V 127 ...
Page 128
... Compare Match Output Unit Compare Output Mode and Waveform Generation ATmega169/V 128 The Compare Output mode (COM2A1:0) bits have two functions. The Waveform Gener- ator uses the COM2A1:0 bits for defining the Output Compare (OC2A) state at the next compare match. Also, the COM2A1:0 bits control the OC2A pin output source. Figure 56 shows a simplified schematic of the logic affected by the COM2A1:0 bit setting ...
Page 129
... TOM when the counter is running with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature. If the new value written to OCR2A is lower than the current value of TCNT2, the counter will miss the ATmega169/V OCnx Interrupt Flag Set (COMnx1 ...
Page 130
... Fast PWM Mode ATmega169/V 130 compare match. The counter will then have to count to its maximum value (0xFF) and wrap around starting at 0x00 before the compare match can occur. For generating a waveform output in CTC mode, the OC2A output can be set to toggle its logical level on each compare match by setting the Compare Output mode bits to tog- gle mode (COM2A1 ...
Page 131
... PWM mode is shown on Figure 59. The TCNT2 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes repre- sent compare matches between OCR2A and TCNT2. ATmega169/V f clk_I/O f ...
Page 132
... ATmega169/V 132 Figure 59. Phase Correct PWM Mode, Timing Diagram TCNTn OCnx OCnx Period 1 The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches BOT- TOM. The Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM value. ...
Page 133
... Figure 61 shows the same timing data, but with the prescaler enabled. Figure 61. Timer/Counter Timing Diagram, with Prescaler (f clk I/O clk Tn (clk /8) I/O TCNTn MAX - 1 TOVn Figure 62 shows the setting of OCF2A in all modes except CTC mode. ATmega169/V MAX BOTTOM BOTTOM + 1 /8) clk_I/O MAX BOTTOM BOTTOM + 1 should I/O 133 ...
Page 134
... ATmega169/V 134 Figure 62. Timer/Counter Timing Diagram, Setting of OCF2A, with Prescaler (f clk I/O clk Tn (clk /8) I/O TCNTn OCRnx - 1 OCRnx OCFnx Figure 63 shows the setting of OCF2A and the clearing of TCNT2 in CTC mode. Figure 63. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Prescaler (f ...
Page 135
... CTC Fast PWM Note: 1. The CTC2 and PWM2 bit definition names are now obsolete. Use the WGM21:0 def- initions. However, the functionality and location of these bits are compatible with previous versions of the timer. ATmega169 COM2A0 WGM21 CS22 CS21 R/W R/W ...
Page 136
... ATmega169/V 136 • Bit 5:4 – COM2A1:0: Compare Match Output Mode A These bits control the Output Compare pin (OC2A) behavior. If one or both of the COM2A1:0 bits are set, the OC2A output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit cor- responding to OC2A pin must be set in order to enable the output driver ...
Page 137
... Initial Value The Output Compare Register A contains an 8-bit value that is continuously compared with the counter value (TCNT2). A match can be used to generate an Output Compare interrupt generate a waveform output on the OC2A pin. ATmega169/V Description No clock source (Timer/Counter stopped). clk /(No prescaling) T2S clk /8 (From prescaler) ...
Page 138
... Asynchronous operation of the Timer/Counter Asynchronous Status Register – ASSR ATmega169/V 138 Bit – – – Read/Write Initial Value • Bit 4 – EXCLK: Enable External Clock Input When EXCLK is written to one, and asynchronous clock is selected, the external clock input buffer is enabled and an external clock can be input on Timer Oscillator 1 (TOSC1) pin instead kHz crystal ...
Page 139
... Power-down or Standby mode. The contents of all Timer/Counter2 Registers must be considered lost after a wake-up from Power- down or Standby mode due to unstable clock signal upon start-up, no matter whether the Oscillator is in use or a clock signal is applied to the TOSC1 pin. ATmega169/V 139 ...
Page 140
... Timer/Counter2 Interrupt Mask Register – TIMSK2 ATmega169/V 140 • Description of wake up from Power-save or ADC Noise Reduction mode when the timer is clocked asynchronously: When the interrupt condition is met, the wake up process is started on the following cycle of the timer clock, that is, the timer is always advanced by at least one before the processor can read the counter value. ...
Page 141
... Alternatively, TOV2 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE2A (Timer/Counter2 Overflow Interrupt Enable), and TOV2 are set (one), the Timer/Counter2 Overflow interrupt is executed. In PWM mode, this bit is set when Timer/Counter2 changes counting direction at 0x00. ATmega169 – ...
Page 142
... Timer/Counter Prescaler General Timer/Counter Control Register – GTCCR ATmega169/V 142 Figure 64. Prescaler for Timer/Counter2 clk clk I/O T2S Clear TOSC1 AS2 PSR2 CS20 CS21 CS22 The clock source for Timer/Counter2 is named clk the main system I/O clock clk . By setting the AS2 bit in ASSR, Timer/Counter2 is asyn- IO chronously clocked from the TOSC1 pin ...
Page 143
... Serial Peripheral Interface – SPI 2514P–AVR–07/06 The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega169 and peripheral devices or between several AVR devices. The ATmega169 SPI includes the following features: • Full-duplex, Three-wire Synchronous Data Transfer • ...
Page 144
... ATmega169/V 144 each data packet, the Master will synchronize the Slave by pulling high the Slave Select, SS, line. When configured as a Master, the SPI interface has no automatic control of the SS line. This must be handled by user software before communication can start. When this is done, writing a byte to the SPI Data Register starts the SPI clock generator, and the hardware shifts the eight bits into the Slave ...
Page 145
... Data Direction Register controlling the SPI pins. DD_MOSI, DD_MISO and DD_SCK must be replaced by the actual data direction bits for these pins. E.g. if MOSI is placed on pin PB5, replace DD_MOSI with DDB5 and DDR_SPI with DDRB. (1) Assembly Code Example ATmega169/V Direction, Slave SPI Input User Defined Input ...
Page 146
... ATmega169/V 146 SPI_MasterInit: ; Set MOSI and SCK output, all others input ldi r17,(1<<DD_MOSI)|(1<<DD_SCK) out DDR_SPI,r17 ; Enable SPI, Master, set clock rate fck/16 ldi r17,(1<<SPE)|(1<<MSTR)|(1<<SPR0) out SPCR,r17 ret SPI_MasterTransmit: ; Start transmission of data (r16) ...
Page 147
... SPI_SlaveInit(void Set MISO output, all others input */ DDR_SPI = (1<<DD_MISO); /* Enable SPI */ SPCR = (1<<SPE); } char SPI_SlaveReceive(void Wait for reception complete */ while(!(SPSR & (1<<SPIF))) ; /* Return Data Register */ return SPDR; } Note: 1. See “About Code Examples” on page 6. ATmega169/V 147 ...
Page 148
... SS Pin Functionality Slave Mode Master Mode SPI Control Register – SPCR ATmega169/V 148 When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO becomes an output if configured so by the user. All other pins are inputs. When SS is driven high, all pins are inputs, and the SPI is passive, which means that it will not receive incoming data ...
Page 149
... SPR0 have no effect on the Slave. The relationship between SCK and the Oscillator Clock frequency f is shown in the following table: osc Table 69. Relationship Between SCK and the Oscillator Frequency SPI2X SPR1 ATmega169/V Leading Edge Trailing Edge Rising Falling Leading Edge Trailing Edge Sample Setup Sample SPR0 SCK Frequency osc osc f ...
Page 150
... SPI is in Master mode (see Table 69). This means that the minimum SCK period will be two CPU clock periods. When the SPI is configured as Slave, the SPI is only guaran- teed to work lower. osc The SPI interface on the ATmega169 is also used for program memory and EEPROM downloading or uploading. See page 281 for serial programming and verification. Bit 7 6 ...
Page 151
... SCK (CPOL = 0) mode 1 SCK (CPOL = 1) mode 3 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS MSB first (DORD = 0) MSB LSB first (DORD = 1) LSB ATmega169/V Trailing eDge Setup (Falling) Sample (Falling) Setup (Rising) Sample (Rising) Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 ...
Page 152
... USART Overview ATmega169/V 152 The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART highly flexible serial communication device. The main features are: • Full Duplex Operation (Independent Serial Receive and Transmit Registers) • Asynchronous or Synchronous Operation • Master or Slave Clocked Synchronous Operation • ...
Page 153
... U2X found in the UCSRA Register. When using synchronous mode (UMSEL = 1), the Data Direction Register for the XCK pin (DDR_XCK) controls whether the clock source is internal (Master mode) or external (Slave mode). The XCK pin is only active when using synchronous mode. Figure 70 shows a block diagram of the clock generation logic. ATmega169/V 153 ...
Page 154
... Internal Clock Generation – The Baud Rate Generator ATmega169/V 154 Figure 70. Clock Generation Logic, Block Diagram UBRR fosc UBRR+1 Prescaling Down-Counter OSC Sync Register xcki XCK xcko Pin DDR_XCK Signal description: txclk Transmitter clock (Internal Signal). rxclk Receiver base clock (Internal Signal). ...
Page 155
... Receiver. This process introduces a two CPU clock period delay and therefore the max- imum external XCK clock frequency is limited by the following equation: Note that f depends on the stability of the system clock source therefore recom- osc mended to add some margin to avoid possible loss of data due to frequency variations. ATmega169/V Equation for Calculating (1) Baud Rate UBRR Value f ...
Page 156
... Synchronous Clock Operation When synchronous mode is used (UMSEL = 1), the XCK pin will be used as either clock Frame Formats ATmega169/V 156 input (Slave) or clock output (Master). The dependency between the clock edges and data sampling or data change is the same. The basic principle is that data input (on RxD) is sampled at the opposite XCK clock edge of the edge the data output (TxD) is changed ...
Page 157
... TXC Flag can be used to check that the Transmitter has completed all transfers, and the RXC Flag can be used to check that there are no unread data in the receive buffer. Note that the TXC Flag must be cleared before each transmission (before UDR is written used for this purpose. ATmega169/V ⊕ … ⊕ ...
Page 158
... ATmega169/V 158 The following simple USART initialization code examples show one assembly and one C function that are equal in functionality. The examples assume asynchronous opera- tion using polling (no interrupts enabled) and a fixed frame format. The baud rate is given as a function parameter. For the assembly code, the baud rate parameter is assumed to be stored in the r17:r16 Registers ...
Page 159
... See “About Code Examples” on page 6. The function simply waits for the transmit buffer to be empty by checking the UDRE Flag, before loading it with new data to be transmitted. If the Data Register Empty inter- rupt is utilized, the interrupt routine writes the data into the buffer. ATmega169/V 159 ...
Page 160
... Sending Frames with 9 Data Bit ATmega169/V 160 If 9-bit characters are used (UCSZ = 7), the ninth bit must be written to the TXB8 bit in UCSRB before the low byte of the character is written to UDR. The following code examples show a transmit function that handles 9-bit characters. For the assembly code, the data to be sent is assumed to be stored in registers R17:R16 ...
Page 161
... The disabling of the Transmitter (setting the TXEN to zero) will not become effective until ongoing and pending transmissions are completed, i.e., when the Transmit Shift Register and Transmit Buffer Register do not contain data to be transmitted. When dis- abled, the Transmitter will no longer override the TxD pin. ATmega169/V 161 ...
Page 162
... Data Reception – The USART Receiver Receiving Frames with Data Bits ATmega169/V 162 The USART Receiver is enabled by writing the Receive Enable (RXEN) bit in the UCSRB Register to one. When the Receiver is enabled, the normal pin operation of the RxD pin is overridden by the USART and given the function as the Receiver’s serial input ...
Page 163
... UCSRA; resh = UCSRB; resl = UDR error, return - status & (1<<FE)|(1<<DOR)|(1<<UPE) ) return -1; /* Filter the 9th bit, then return */ resh = (resh >> 1) & 0x01; return ((resh << resl); } Note: 1. See “About Code Examples” on page 6. ATmega169/V 163 ...
Page 164
... Receive Compete Flag and Interrupt Receiver Error Flags ATmega169/V 164 The receive function example reads all the I/O Registers into the Register File before any computation is done. This gives an optimal receive buffer utilization since the buffer location read will be free to accept new data as early as possible. ...
Page 165
... The data recovery logic samples and low pass filters each incoming bit, thereby improv- ing the noise immunity of the Receiver. The asynchronous reception operational range depends on the accuracy of the internal baud rate clock, the rate of the incoming frames, and the frame size in number of bits. ATmega169/V 165 ...
Page 166
... Asynchronous Clock Recovery Asynchronous Data Recovery ATmega169/V 166 The clock recovery logic synchronizes internal clock to the incoming serial frames. Fig- ure 73 illustrates the sampling process of the start bit of an incoming frame. The sample rate is 16 times the baud rate for Normal mode, and eight times the baud rate for Double Speed mode ...
Page 167
... Table 72 and Table 73 list the maximum receiver baud rate error that can be tolerated. Note that Normal Speed mode has higher toleration of baud rate variations. ATmega169/V STOP 1 (A) (B) 5 ...
Page 168
... ATmega169/V 168 Table 72. Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode (U2X = (Data+Parity Bit) R (%) R slow 5 93.20 106.67 6 94.12 105.79 7 94.81 105.11 8 95.36 104.58 9 95.81 104.14 10 96.17 103.78 Table 73. Recommended Maximum Receiver Baud Rate Error for Double Speed Mode ...
Page 169
... Do not use Read-Modify-Write instructions (SBI and CBI) to set or clear the MPCM bit. The MPCM bit shares the same I/O location as the TXC Flag and this might accidentally be cleared when using SBI or CBI instructions. ATmega169/V 169 ...
Page 170
... USART Register Description USART I/O Data Register – UDR USART Control and Status Register A – UCSRA ATmega169/V 170 Bit Read/Write R/W R/W R/W Initial Value The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers share the same I/O address referred to as USART Data Register or UDR. The Transmit Data Buffer Register (TXB) will be the destination for data written to the UDR Register location ...
Page 171
... This bit enables the Multi-processor Communication mode. When the MPCM bit is writ- ten to one, all the incoming frames received by the USART Receiver that do not contain address information will be ignored. The Transmitter is unaffected by the MPCM setting. For more detailed information see “Multi-processor Communication Mode” on page 169. ATmega169/V 171 ...
Page 172
... USART Control and Status Register B – UCSRB ATmega169/V 172 Bit RXCIE TXCIE UDRIE Read/Write R/W R/W R/W Initial Value • Bit 7 – RXCIE: RX Complete Interrupt Enable Writing this bit to one enables interrupt on the RXC Flag. A USART Receive Complete interrupt will be generated only if the RXCIE bit is written to one, the Global Interrupt Flag in SREG is written to one and the RXC bit in UCSRA is set. • ...
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... UPM1 UPM0 • Bit 3 – USBS: Stop Bit Select This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver ignores this setting. Table 76. USBS Bit Settings USBS 0 1 ATmega169 UPM0 USBS UCSZ1 UCSZ0 R/W R/W R/W R Parity Mode ...
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... USART Baud Rate Registers – UBRRL and UBRRH ATmega169/V 174 • Bit 2:1 – UCSZ1:0: Character Size The UCSZ1:0 bits combined with the UCSZ2 bit in UCSRB sets the number of data bits (Character SiZe frame the Receiver and Transmitter use. Table 77. UCSZ Bits Settings ...
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... ATmega169/V BaudRate ⎛ ⎞ Closest Match • ------------------------------------------------------- - 1 100% – ⎝ ⎠ BaudRate f = 2.0000 MHz osc U2X = 1 U2X = 0 UBRR Error UBRR Error 95 0. ...
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... Max. 230.4 kbps 460.8 kbps 1. UBRR = 0, Error = 0.0% ATmega169/V 176 f = 4.0000 MHz osc U2X = 0 U2X = 1 Error UBRR Error UBRR 0.0% 103 0.2% 207 0.0% 51 0.2% 103 0.0% 25 0.2% 51 0. ...
Page 177
... Mbps 691.2 kbps ATmega169/V MHz f = 14.7456 MHz osc U2X = 1 U2X = 0 Error UBRR Error 575 0.0% 383 0.0% 287 0.0% 191 0.0% 143 0.0% 95 0. ...
Page 178
... Max. 1 Mbps 1. UBRR = 0, Error = 0.0% ATmega169/V 178 f = 18.4320 MHz osc U2X = 0 Error UBRR Error UBRR 0.0% 479 0.0% -0.1% 239 0.0% 0.2% 119 0.0% -0.1% 79 0.0% 0.2% 59 0.0% 0.6% 39 0.0% ...
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... Two-wire Start Condition Detector with Interrupt Capability A simplified block diagram of the USI is shown on Figure 76. For the actual placement of I/O pins, refer to “Pinout ATmega169” on page 2. CPU accessible I/O Registers, includ- ing I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the “ ...
Page 180
... Functional Descriptions Three-wire Mode ATmega169/V 180 The Two-wire clock control unit can generate an interrupt when a start condition is detected on the Two-wire bus. It can also generate wait states by holding the clock pin low after a start condition is detected, or after the counter overflows. The USI Three-wire mode is compliant to the Serial Peripheral Interface (SPI) mode 0 and 1, but does not have the slave select (SS) pin functionality ...
Page 181
... The second and third instructions clears the USI Counter Overflow Flag and the USI counter value. The fourth and fifth instruction set Three-wire mode, positive edge Shift Register clock, count at USITC strobe, and toggle USCK. The loop is repeated 16 times. ATmega169/V 181 ...
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... SPI Slave Operation Example ATmega169/V 182 The following code demonstrates how to use the USI module as a SPI Master with max- imum speed (fsck = fck/4): SPITransfer_Fast: sts USIDR,r16 ldi r16,(1<<USIWM0)|(0<<USICS0)|(1<<USITC) ldi r17,(1<<USIWM0)|(0<<USICS0)|(1<<USITC)|(1<<USICLK) sts USICR,r16 ...
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... The clock is generated by the master by toggling the USCK pin via the PORT Register. The data direction is not given by the physical layer. A protocol, like the one used by the TWI-bus, must be implemented to control the data flow. ATmega169/V SDA Bit1 Bit0 ...
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... ATmega169/V 184 Figure 80. Two-wire Mode, Typical Timing Diagram SDA SCL ADDRESS R Referring to the timing diagram (Figure 80.), a bus transfer involves the following steps: 1. The a start condition is generated by the Master by forcing the SDA low line while the SCL line is high (A). SDA can be forced low either by writing a zero to bit 7 of the Shift Register setting the corresponding bit in the PORT Register to zero ...
Page 185
... Match, or directly by software using the USICLK strobe bit. Note that even when no wire mode is selected (USIWM1.. both the external data input (DI/SDA) and the external clock input (USCK/SCL) can still be used by the Shift Register. ATmega169/V /4. This is also the maximum data transmit CK ...
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... USI Status Register – USISR ATmega169/V 186 The output pin in use SDA depending on the wire mode, is connected via the out- put latch to the most significant bit (bit 7) of the Data Register. The output latch is open (transparent) during the first half of a serial clock cycle when an external clock source is selected (USICS1 = 1), and constantly open when an internal clock source is used (USICS1 = 0) ...
Page 187
... Data and clock inputs are not affected by the mode selected and will always have the same function. The counter and Shift Register can therefore be clocked externally, and data input sampled, even when outputs are disabled. The relations between USIWM1..0 and the USI operation is summarized in Table 83. ATmega169 ...
Page 188
... ATmega169/V 188 Table 83. Relations between USIWM1..0 and the USI Operation USIWM1 USIWM0 Description 0 0 Outputs, clock hold, and start detector disabled. Port pins operates as normal Three-wire mode. Uses DO, DI, and USCK pins. The Data Output (DO) pin overrides the corresponding bit in the PORT Register in this mode ...
Page 189
... When an external clock source is selected (USICS1 = 1) and the USICLK bit is set to one, writing to the USITC strobe bit will directly clock the 4-bit counter. This allows an early detection of when the transfer is done when operating as a master device. ATmega169/V 4-bit Counter Clock Source ...
Page 190
... ADC Control and Status Register B – ADCSRB Analog Comparator Control and Status Register – ACSR ATmega169/V 190 The Analog Comparator compares the input values on the positive pin AIN0 and nega- tive pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator output, ACO, is set. The comparator’ ...
Page 191
... Comparator Interrupt on Falling Output Edge Comparator Interrupt on Rising Output Edge. When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be dis- abled by clearing its Interrupt Enable bit in the ACSR Register. Otherwise an interrupt can occur when the bits are changed. ATmega169/V 191 ...
Page 192
... Analog Comparator Multiplexed Input Digital Input Disable Register 1 – DIDR1 ATmega169/V 192 It is possible to select any of the ADC7..0 pins to replace the negative input to the Ana- log Comparator. The ADC multiplexer is used to select this input, and consequently, the ADC must be switched off to utilize this feature. If the Analog Comparator Multiplexer Enable bit (ACME in ADCSRB) is set and the ADC is switched off (ADEN in ADCSRA is zero), MUX2 ...
Page 193
... Interrupt on ADC Conversion Complete • Sleep Mode Noise Canceler The ATmega169 features a 10-bit successive approximation ADC. The ADC is con- nected to an 8-channel Analog Multiplexer which allows eight single-ended voltage inputs constructed from the pins of Port F. The single-ended voltage inputs refer to 0V (GND) ...
Page 194
... Operation ATmega169/V 194 Figure 83. Analog to Digital Converter Block Schematic 8-BIT DATA BUS ADC MULTIPLEXER SELECT (ADMUX) MUX DECODER AVCC INTERNAL REFERENCE AREF GND BANDGAP REFERENCE ADC7 ADC6 POS. ADC5 INPUT MUX ADC4 ADC3 ADC2 ADC1 ADC0 NEG. INPUT MUX The ADC converts an analog input voltage to a 10-bit digital value through successive approximation ...
Page 195
... ADC will perform successive conversions independently of whether the ADC Interrupt Flag, ADIF is cleared or not. If Auto Triggering is enabled, single conversions can be started by writing ADSC in ADCSRA to one. ADSC can also be used to determine if a conversion is in progress. ATmega169/V PRESCALER START ADATE CONVERSION ...
Page 196
... Prescaling and Conversion Timing ATmega169/V 196 The ADSC bit will be read as one during a conversion, independently of how the conver- sion was started. Figure 85. ADC Prescaler ADEN START CK ADPS0 ADPS1 ADPS2 By default, the successive approximation circuitry requires an input clock frequency between 50 kHz and 200 kHz to get maximum resolution lower resolution than 10 bits is needed, the input clock frequency to the ADC can be higher than 200 kHz to get a higher sample rate ...
Page 197
... Sample & Hold MUX and REFS Update Figure 88. ADC Timing Diagram, Auto Triggered Conversion Cycle Number ADC Clock Trigger Source ADATE ADIF ADCH ADCL Sample & Prescaler Hold Reset MUX and REFS Update ATmega169/V First Conversion Conversion Sample & Hold Complete One Conversion ...
Page 198
... ATmega169/V 198 Figure 89. ADC Timing Diagram, Free Running Conversion One Conversion 11 Cycle Number ADC Clock ADSC ADIF ADCH ADCL Conversion Complete Table 87. ADC Conversion Time Condition First conversion Normal conversions, single ended Auto Triggered conversions Next Conversion Sign and MSB of Result LSB of Result Sample & ...
Page 199
... If the user has a fixed voltage source connected to the AREF pin, the user may not use the other reference voltage options in the application, as they will be shorted to the ATmega169/V ) indicates the conversion range for the ADC. REF will result in codes close to 0x3FF. V REF ) through an internal buffer ...
Page 200
... ADC Noise Canceler Analog Input Circuitry ATmega169/V 200 external voltage external voltage is applied to the AREF pin, the user may switch between AVCC and 1.1V as reference selection. The first ADC conversion result after switching reference voltage source may be inaccurate, and the user is advised to dis- card this result ...