ATMEGA169-16AI Atmel, ATMEGA169-16AI Datasheet - Page 33

• Manufacturer Part Number: ATMEGA169-16AI
• Description: IC AVR MCU 16K 16MHZ IND TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA169-16AI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• For Use With: ATAVRBFLY - KIT EVALUATION AVR BUTTERFLYATSTK502 - MOD EXPANSION AVR STARTER 500
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Idle Mode
ADC Noise Reduction
Mode
Power-down Mode
Power-save Mode
2514P–AVR–07/06
When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter
Idle mode, stopping the CPU but allowing LCD controller, the SPI, USART, Analog
Comparator, ADC, USI, Timer/Counters, Watchdog, and the interrupt system to con-
tinue operating. This sleep mode basically halts clk
other clocks to run.
Idle mode enables the MCU to wake up from external triggered interrupts as well as
internal ones like the Timer Overflow and USART Transmit Complete interrupts. If
wake-up from the Analog Comparator interrupt is not required, the Analog Comparator
can be powered down by setting the ACD bit in the Analog Comparator Control and Sta-
tus Register – ACSR. This will reduce power consumption in Idle mode. If the ADC is
enabled, a conversion starts automatically when this mode is entered.
When the SM2..0 bits are written to 001, the SLEEP instruction makes the MCU enter
ADC Noise Reduction mode, stopping the CPU but allowing the ADC, the external inter-
rupts, the USI start condition detection, Timer/Counter2, LCD Controller, and the
Watchdog to continue operating (if enabled). This sleep mode basically halts clk
clk
This improves the noise environment for the ADC, enabling higher resolution measure-
ments. If the ADC is enabled, a conversion starts automatically when this mode is
entered. Apart form the ADC Conversion Complete interrupt, only an External Reset, a
Watchdog Reset, a Brown-out Reset, an LCD controller interrupt, USI start condition
interrupt, a Timer/Counter2 interrupt, an SPM/EEPROM ready interrupt, an external
level interrupt on INT0 or a pin change interrupt can wake up the MCU from ADC Noise
Reduction mode.
When the SM2..0 bits are written to 010, the SLEEP instruction makes the MCU enter
Power-down mode. In this mode, the external Oscillator is stopped, while the external
interrupts, the USI start condition detection, and the Watchdog continue operating (if
enabled). Only an External Reset, a Watchdog Reset, a Brown-out Reset, USI start con-
dition interrupt, an external level interrupt on INT0, or a pin change interrupt can wake
up the MCU. This sleep mode basically halts all generated clocks, allowing operation of
asynchronous modules only.
Note that if a level triggered interrupt is used for wake-up from Power-down mode, the
changed level must be held for some time to wake up the MCU. Refer to “External Inter-
rupts” on page 51 for details.
When waking up from Power-down mode, there is a delay from the wake-up condition
occurs until the wake-up becomes effective. This allows the clock to restart and become
stable after having been stopped. The wake-up period is defined by the same CKSEL
Fuses that define the Reset Time-out period, as described in “Clock Sources” on page
24.
When the SM2..0 bits are written to 011, the SLEEP instruction makes the MCU enter
Power-save mode. This mode is identical to Power-down, with one exception:
If Timer/Counter2 and/or the LCD controller are enabled, they will keep running during
sleep. The device can wake up from either Timer Overflow or Output Compare event
from Timer/Counter2 if the corresponding Timer/Counter2 interrupt enable bits are set in
TIMSK2, and the Global Interrupt Enable bit in SREG is set. It can also wake up from an
LCD controller interrupt.
If neither Timer/Counter2 nor the LCD controller is running, Power-down mode is rec-
ommended instead of Power-save mode.
CPU
, and clk
FLASH
, while allowing the other clocks to run.
CPU
and clk
ATmega169/V
FLASH
, while allowing the
I/O
33
,