ATMEGA169-16AI Atmel, ATMEGA169-16AI Datasheet - Page 229

• Manufacturer Part Number: ATMEGA169-16AI
• Description: IC AVR MCU 16K 16MHZ IND TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA169-16AI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• For Use With: ATAVRBFLY - KIT EVALUATION AVR BUTTERFLYATSTK502 - MOD EXPANSION AVR STARTER 500
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Using the Boundary-
scan Chain
Using the On-chip Debug
System
2514P–AVR–07/06
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As shown in the state diagram, the Run-Test/Idle state need not be entered between
selecting JTAG instruction and using Data Registers, and some JTAG instructions may
select certain functions to be performed in the Run-Test/Idle, making it unsuitable as an
Idle state.
Note:
For detailed information on the JTAG specification, refer to the literature listed in “Bibli-
ography” on page 231.
A complete description of the Boundary-scan capabilities are given in the section “IEEE
1149.1 (JTAG) Boundary-scan” on page 232.
As shown in Figure 105, the hardware support for On-chip Debugging consists mainly of
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All read or modify/write operations needed for implementing the Debugger are done by
applying AVR instructions via the internal AVR CPU Scan Chain. The CPU sends the
result to an I/O memory mapped location which is part of the communication interface
between the CPU and the JTAG system.
The Break Point Unit implements Break on Change of Program Flow, Single Step
Break, two Program Memory Break Points, and two combined Break Points. Together,
the four Break Points can be configured as either:
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A debugger, like the AVR Studio, may however use one or more of these resources for
its internal purpose, leaving less flexibility to the end-user.
state. The Exit-IR, Pause-IR, and Exit2-IR states are only used for navigating the
state machine.
At the TMS input, apply the sequence 1, 0, 0 at the rising edges of TCK to enter the
Shift Data Register – Shift-DR state. While in this state, upload the selected Data
Register (selected by the present JTAG instruction in the JTAG Instruction Register)
from the TDI input at the rising edge of TCK. In order to remain in the Shift-DR state,
the TMS input must be held low during input of all bits except the MSB. The MSB of
the data is shifted in when this state is left by setting TMS high. While the Data
Register is shifted in from the TDI pin, the parallel inputs to the Data Register
captured in the Capture-DR state is shifted out on the TDO pin.
Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. If the selected
Data Register has a latched parallel-output, the latching takes place in the Update-
DR state. The Exit-DR, Pause-DR, and Exit2-DR states are only used for navigating
the state machine.
A scan chain on the interface between the internal AVR CPU and the internal
peripheral units.
Break Point unit.
Communication interface between the CPU and JTAG system.
4 single Program Memory Break Points.
3 Single Program Memory Break Point + 1 single Data Memory Break Point.
2 single Program Memory Break Points + 2 single Data Memory Break Points.
2 single Program Memory Break Points + 1 Program Memory Break Point with mask
(“range Break Point”).
2 single Program Memory Break Points + 1 Data Memory Break Point with mask
(“range Break Point”).
Independent of the initial state of the TAP Controller, the Test-Logic-Reset state can
always be entered by holding TMS high for five TCK clock periods.
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