ATMEGA169-16AI Atmel, ATMEGA169-16AI Datasheet - Page 211

• Manufacturer Part Number: ATMEGA169-16AI
• Description: IC AVR MCU 16K 16MHZ IND TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA169-16AI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• For Use With: ATAVRBFLY - KIT EVALUATION AVR BUTTERFLYATSTK502 - MOD EXPANSION AVR STARTER 500
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

LCD Clock Sources
LCD Prescaler
LCD Memory
2514P–AVR–07/06
Figure 97. LCD Module Block Diagram
The LCD Controller can be clocked by an internal synchronous or an external asynchro-
nous clock source. The clock source clk
When the LCDCS bit in the LCDCRB Register is written to logic one, the clock source is
taken from the TOSC1 pin.
The clock source must be stable to obtain accurate LCD timing and hence minimize DC
voltage offset across LCD segments.
The prescaler consist of a 12-bit ripple counter and a 1- to 8-clock divider. The
LCDPS2:0 bits selects clk
If a finer resolution rate is required, the LCDCD2:0 bits can be used to divide the clock
further by 1 to 8.
Output from the clock divider clk
The display memory is available through I/O Registers grouped for each common termi-
nal. When a bit in the display memory is written to one, the corresponding segment is
energized (on), and non-energized when a bit in the display memory is written to zero.
To energize a segment, an absolute voltage above a certain threshold must be applied.
This is done by letting the output voltage on corresponding COM pin and SEG pin have
opposite phase. For display with more than one common, one (1/2 bias) or two (1/3
bias) additional voltage levels must be applied. Otherwise, non-energized segments on
COM0 would be energized for all non-selected common.
D
A
T
A
B
U
S
LCDCCR
LCDFRR
LCDCRA
LCDCRB
TOSC
LCDDR 18 -15
LCDDR 13 -10
clk
LCDDR 8 - 5
LCDDR 3 - 0
i/o
lcdcc3:0
0
1
lcdcs
LCD
Configuration
LATCH
array
Display
clk
divided by 16, 64, 128, 256, 512, 1024, 2048, or 4096.
LCD
Contrast Controller/
Power Supply
LCD_PS
lcdps2:0
lcdcd2:0
MUX
25 x
4:1
is used as clock source for the LCD timing.
LCD
is by default equal to the system clock, clk
Divide by 1 to 8
12-bit Prescaler
LCD_voltage_ok
Multiplexer
LCD Ouput
Decoder
Timing
Clock
LCD
clk
LCD_PS
LCD Buffer/
Driver
LCD
CAP
ATmega169/V
1/3 V
1/2 V
2/3 V
V
LCD
LCD
LCD
LCD
Analog
Switch
Array
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
COM0
COM1
COM2
COM3
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
211
I/O
.