DSPIC30F2010-30I/SO Microchip Technology, DSPIC30F2010-30I/SO Datasheet - Page 49

• Manufacturer Part Number: DSPIC30F2010-30I/SO
• Description: IC DSPIC MCU/DSP 12K 28SOIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F2010-30I/SO

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 12KB (4K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 20
• Flash Memory Size: 12KB
• Supply Voltage Range: 2.5V To 5.5V
• Package: 28SOIC W
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 30 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 20
• Interface Type: I2C/SPI/UART
• On-chip Adc: 6-chx10-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification

11.10 Reading Code Memory
Reading from code memory is performed by executing
a series of TBLRD instructions and clocking out the data
using the REGOUT command. To ensure efficient
execution and facilitate verification on the programmer,
four instruction words are read from the device at a
time.
Table 11-10
reading code memory. In Step 1, the Reset vector is
exited. In Step 2, the 24-bit starting source address for
reading is loaded into the TBLPAG and W6 registers.
The upper byte of the starting source address is stored
to TBLPAG, while the lower 16 bits of the source
address are stored to W6.
TABLE 11-10: SERIAL INSTRUCTION EXECUTION FOR READING CODE MEMORY
© 2010 Microchip Technology Inc.
Step 1: Exit the Reset vector.
0000
0000
0000
Step 2: Initialize TBLPAG and the read pointer (W6) for TBLRD instruction.
0000
0000
0000
Step 3: Initialize the write pointer (W7) and store the next four locations of code memory to W0:W5.
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
Command
(Binary)
shows the ICSP programming details for
(Hexadecimal)
040100
040100
000000
200xx0
880190
2xxxx6
EB0380
000000
BA1B96
000000
000000
BADBB6
000000
000000
BADBD6
000000
000000
BA1BB6
000000
000000
BA1B96
000000
000000
BADBB6
000000
000000
BADBD6
000000
000000
BA0BB6
000000
000000
Data
GOTO 0x100
GOTO 0x100
NOP
MOV
MOV
MOV
CLR
NOP
TBLRDL
NOP
NOP
TBLRDH.B
NOP
NOP
TBLRDH.B
NOP
NOP
TBLRDL
NOP
NOP
TBLRDL
NOP
NOP
TBLRDH.B
NOP
NOP
TBLRDH.B
NOP
NOP
TBLRDL
NOP
NOP
#<SourceAddress23:16>, W0
W0, TBLPAG
#<SourceAddress15:0>, W6
W7
[W6], [W7++]
[W6++], [W7++]
[++W6], [W7++]
[W6++], [W7++]
[W6], [W7++]
[W6++], [W7++]
[++W6], [W7++]
[W6++], [W7]
To minimize the reading time, the packed instruction
word format that was utilized for writing is also used for
reading (see
W7 is initialized, and four instruction words are read
from code memory and stored to working registers
W0:W5. In Step 4, the four instruction words are
clocked out of the device from the VISI register using
the REGOUT command. In Step 5, the internal PC is
reset to 0x100, as a precautionary measure, to prevent
the PC from incrementing into unimplemented memory
when large devices are being read. Lastly, in Step 6,
Steps 3-5 are repeated until the desired amount of
code memory is read.
Description
Figure
11-5). In Step 3, the write pointer
DS70102K-page 49