AT91FR40162S-CJ Atmel, AT91FR40162S-CJ Datasheet - Page 120

• Manufacturer Part Number: AT91FR40162S-CJ
• Description: IC ARM MCU FLASH 1K 121BGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91FR40162S-CJ

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 75MHz
• Connectivity: EBI/EMI, UART/USART
• Peripherals: WDT
• Number Of I /o: 32
• Program Memory Size: 2MB (1M x 16)
• Program Memory Type: FLASH
• Ram Size: 256K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 121-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

17.4
17.4.1
17.4.2
120
Receiver
AT91FR40162S Preliminary
Asynchronous Receiver
Synchronous Receiver
The USART is configured for asynchronous operation when SYNC = 0 (bit 7 of US_MR). In
Asynchronous Mode, the USART detects the start of a received character by sampling the RXD
signal until it detects a valid start bit. A low level (space) on RXD is interpreted as a valid start bit
if it is detected for more than 7 cycles of the sampling clock, which is 16 times the baud rate.
Hence a space which is longer than 7/16 of the bit period is detected as a valid start bit. A space
which is 7/16 of a bit period or shorter is ignored and the receiver continues to wait for a valid
start bit.
When a valid start bit has been detected, the receiver samples the RXD at the theoretical mid-
point of each bit. It is assumed that each bit lasts 16 cycles of the sampling clock (one bit period)
so the sampling point is 8 cycles (0.5 bit periods) after the start of the bit. The first sampling point
is therefore 24 cycles (1.5 bit periods) after the falling edge of the start bit was detected. Each
subsequent bit is sampled 16 cycles (1 bit period) after the previous one.
Figure 17-3. Asynchronous Mode: Start Bit Detection
Figure 17-4. Asynchronous Mode: Character Reception
When configured for synchronous operation (SYNC = 1), the receiver samples the RXD signal
on each rising edge of the Baud Rate clock. If a low level is detected, it is considered as a start.
Data bits, parity bit and stop bit are sampled and the receiver waits for the next start bit. See
example in
Rate Clock
Example: 8-bit, parity enabled 1 stop
16 x Baud
Sampling
Sampling
RXD
RXD
Figure
periods
0.5 bit
True Start Detection
17-5.
period
1 bit
D0
D1
True Start
Detection
D2
D3
D4
D5
D6
D7
6174B–ATARM–07-Nov-05
Parity Bit
Stop Bit
D0