AT91FR40162S-CJ Atmel, AT91FR40162S-CJ Datasheet - Page 28
AT91FR40162S-CJ
Manufacturer Part Number
AT91FR40162S-CJ
Description
IC ARM MCU FLASH 1K 121BGA
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91FR40162S-CJ.pdf
(210 pages)
Specifications of AT91FR40162S-CJ
Core Processor
ARM7
Core Size
16/32-Bit
Speed
75MHz
Connectivity
EBI/EMI, UART/USART
Peripherals
WDT
Number Of I /o
32
Program Memory Size
2MB (1M x 16)
Program Memory Type
FLASH
Ram Size
256K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
121-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT91FR40162S-CJ
Manufacturer:
ATMEL
Quantity:
455
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Figure 10-11. Early Read Wait State
Write Cycle
Early Read Wait
Read Cycle
MCKI
ADDR
NCS
NRD
NWE
10.8
Write Data Hold Time
During write cycles in both protocols, output data becomes valid after the falling edge of the
NWE signal and remains valid after the rising edge of NWE, as illustrated in
Figure
10-12. The
external NWE waveform (on the NWE pin) is used to control the output data timing to guarantee
this operation.
It is therefore necessary to avoid excessive loading of the NWE pins, which could delay the write
signal too long and cause a contention with a subsequent read cycle in standard protocol.
Figure 10-12. Data Hold Time
MCK
ADDR
NWE
Data Output
In early read protocol the data can remain valid longer than in standard read protocol due to the
additional wait cycle which follows a write access.
AT91FR40162S Preliminary
28
6174B–ATARM–07-Nov-05
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