AT91FR40162S-CJ Atmel, AT91FR40162S-CJ Datasheet - Page 29

• Manufacturer Part Number: AT91FR40162S-CJ
• Description: IC ARM MCU FLASH 1K 121BGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91FR40162S-CJ

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 75MHz
• Connectivity: EBI/EMI, UART/USART
• Peripherals: WDT
• Number Of I /o: 32
• Program Memory Size: 2MB (1M x 16)
• Program Memory Type: FLASH
• Ram Size: 256K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 121-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

10.9
10.9.1
10.9.2
6174B–ATARM–07-Nov-05
Wait States
Standard Wait States
Data Float Wait State
The EBI can automatically insert wait states. The different types of wait states are listed below:
Each chip select can be programmed to insert one or more wait states during an access on the
corresponding device. This is done by setting the WSE field in the corresponding EBI_CSR. The
number of cycles to insert is programmed in the NWS field in the same register.
Below is the correspondence between the number of standard wait states programmed and the
number of cycles during which the NWE pulse is held low:
For each additional wait state programmed, an additional cycle is added.
Figure 10-13. One Wait State Access
Notes:
Some memory devices are slow to release the external bus. For such devices it is necessary to
add wait states (data float waits) after a read access before starting a write access or a read
access to a different external memory.
The Data Float Output Time (t
field of the EBI_CSR register for the corresponding chip select. The value (0 - 7 clock cycles)
indicates the number of data float waits to be inserted and represents the time allowed for the
data output to go high impedance after the memory is disabled.
• Standard wait states
• Data float wait states
• External wait states
• Chip select change wait states
• Early read wait states (see
0 wait states
1 wait state
1. Early Read Protocol
2. Standard Read Protocol
ADDR
NWE
MCK
NRD
NCS
Section 10.7 ”Read Protocols”, on page
1/2 cycle
1 cycle
DF
(1)
) for each external memory device is programmed in the TDF
1 Wait State Access
(2)
AT91FR40162S Preliminary
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