AT91FR40162S-CJ Atmel, AT91FR40162S-CJ Datasheet - Page 26

• Manufacturer Part Number: AT91FR40162S-CJ
• Description: IC ARM MCU FLASH 1K 121BGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91FR40162S-CJ

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 75MHz
• Connectivity: EBI/EMI, UART/USART
• Peripherals: WDT
• Number Of I /o: 32
• Program Memory Size: 2MB (1M x 16)
• Program Memory Type: FLASH
• Ram Size: 256K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 121-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

10.6
10.7
10.7.1
10.7.2
10.7.3
26
Boot on NCS0
Read Protocols
AT91FR40162S Preliminary
Standard Read Protocol
Early Read Protocol
Early Read Wait State
Depending on the device and the BMS pin level during the reset, the user can select either an 8-
bit or 16-bit external memory device connected on NCS0 as the Boot Memory. In this case,
EBI_CSR0 (Chip Select Register 0) is reset at the following configuration for chip select 0:
Byte access type and number of data float time are respectively set to Byte Write Access and 0.
With a non-volatile memory interface, any values can be programmed for these parameters.
Before the remap command, the user can modify the chip select 0 configuration, programming
the EBI_CSR0 with exact boot memory characteristics. the base address becomes effective
after the remap command, but the new number of wait states can be changed immediately. This
is useful if a boot sequence needs to be faster.
The EBI provides two alternative protocols for external memory read access: standard and early
read. The difference between the two protocols lies in the timing of the NRD (read cycle)
waveform.
The protocol is selected by the DRP field in EBI_MCR (Memory Control Register) and is valid for
all memory devices. Standard read protocol is the default protocol after reset.
Note:
Standard read protocol implements a read cycle in which NRD and NWE are similar. Both are
active during the second half of the clock cycle. The first half of the clock cycle allows time to
ensure completion of the previous access as well as the output of address and NCS before the
read cycle begins.
During a standard read protocol, external memory access, NCS is set low and ADDR is valid at
the beginning of the access while NRD goes low only in the second half of the master clock
cycle to avoid bus conflict (see
goes low in the second half of the master clock cycle (see
Early read protocol provides more time for a read access from the memory by asserting NRD at
the beginning of the clock cycle. In the case of successive read cycles in the same memory,
NRD remains active continuously. Since a read cycle normally limits the speed of operation of
the external memory system, early read protocol can allow a faster clock frequency to be used.
However, an extra wait state is required in some cases to avoid contentions on the external bus.
In early read protocol, an early read wait state is automatically inserted when an external write
cycle is followed by a read cycle to allow time for the write cycle to end before the subsequent
read cycle begins (see
grammed wait states (i.e. data float wait).
• 8 wait states (WSE = 1, NWS = 7)
• 8-bit or 16-bit data bus width, depending on BMS
In the following waveforms and descriptions, NRD represents NRD and NOE since the two signals
have the same waveform. Likewise, NWE represents NWE, NWR0 and NWR1 unless NWR0 and
NWR1 are otherwise represented. ADDR represents A0 - A23 and/or A1 - A23.
Figure
10-11). This wait state is generated in addition to any other pro-
Figure
10-9). NWE is the same in both protocols. NWE always
Figure
10-10).
6174B–ATARM–07-Nov-05